From patchwork Tue Oct 6 14:26:53 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 7335071 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id DD54C9F750 for ; Tue, 6 Oct 2015 14:27:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 184D320715 for ; Tue, 6 Oct 2015 14:27:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 422B5206F3 for ; Tue, 6 Oct 2015 14:27:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C8F926E3EC; Tue, 6 Oct 2015 07:27:02 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 7CCE66E3F4 for ; Tue, 6 Oct 2015 07:27:00 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP; 06 Oct 2015 07:27:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,644,1437462000"; d="scan'208";a="820532232" Received: from rosetta.fi.intel.com (HELO rosetta) ([10.237.72.50]) by orsmga002.jf.intel.com with ESMTP; 06 Oct 2015 07:26:59 -0700 Received: by rosetta (Postfix, from userid 1000) id 107DF80098; Tue, 6 Oct 2015 17:26:56 +0300 (EEST) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2015 17:26:53 +0300 Message-Id: <1444141613-11152-13-git-send-email-mika.kuoppala@intel.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1444141613-11152-1-git-send-email-mika.kuoppala@intel.com> References: <1444141613-11152-1-git-send-email-mika.kuoppala@intel.com> Cc: miku@iki.fi Subject: [Intel-gfx] [PATCH 12/12] drm/i915/ivb: Simplify row chicken setup logic X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We always write the ROW_CHICKEN2. Make this more clear by writing it unconditionally. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_pm.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 8bc1d3b..ec77e04 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6685,16 +6685,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) WA_WRITE(MMIO, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); WA_WRITE(MMIO, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); - if (IS_IVB_GT1(dev)) - WA_SET_BIT_MASKED(MMIO, GEN7_ROW_CHICKEN2, - DOP_CLOCK_GATING_DISABLE); - else { - /* must write both registers */ - WA_SET_BIT_MASKED(MMIO, GEN7_ROW_CHICKEN2, - DOP_CLOCK_GATING_DISABLE); + WA_SET_BIT_MASKED(MMIO, GEN7_ROW_CHICKEN2, + DOP_CLOCK_GATING_DISABLE); + + /* must write both registers */ + if (!IS_IVB_GT1(dev)) WA_SET_BIT_MASKED(MMIO, GEN7_ROW_CHICKEN2_GT2, DOP_CLOCK_GATING_DISABLE); - } /* WaForceL3Serialization:ivb */ WA_CLR_BIT(MMIO, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);