diff mbox

[04/12] drm/i915: Move workaround macros to i915_drv.h

Message ID 1444141613-11152-5-git-send-email-mika.kuoppala@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Mika Kuoppala Oct. 6, 2015, 2:26 p.m. UTC 
The plan is to allow workaround list usage outside of
intel_ringbuffer.c, mainly in intel_pm.c where we setup assortment
of workaround registers as part of intel_init_clock_gating().

Move macros to i915_drv.h and export intel_wa_add().
Remove WA_WRITE macro as there are no users of it as of now.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         | 22 ++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 24 ++----------------------
 2 files changed, 24 insertions(+), 22 deletions(-)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1883847..5a04948 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3518,4 +3518,26 @@  static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
 		i915_gem_request_assign(&ring->trace_irq_req, req);
 }
 
+/* Workaround register lists */
+#define WA_REG(addr, mask, val) do { \
+		const int r = intel_wa_add(&dev_priv->lri_workarounds, \
+					   (addr), (mask), (val)); \
+		WARN_ON(r); \
+	} while (0)
+
+#define WA_SET_BIT_MASKED(addr, mask) \
+	WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
+
+#define WA_CLR_BIT_MASKED(addr, mask) \
+	WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
+
+#define WA_SET_FIELD_MASKED(addr, mask, value) \
+	WA_REG(addr, mask, _MASKED_FIELD(mask, value))
+
+#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ((addr)) | (mask))
+#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ((addr)) & ~(mask))
+
+int intel_wa_add(struct i915_workarounds *w,
+		 const u32 addr, const u32 mask, const u32 val);
+
 #endif
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index bc8a8e2..29ae97e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -763,8 +763,8 @@  static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 	return ret;
 }
 
-static int wa_add(struct i915_workarounds *w,
-		  const u32 addr, const u32 mask, const u32 val)
+int intel_wa_add(struct i915_workarounds *w,
+		 const u32 addr, const u32 mask, const u32 val)
 {
 	const u32 idx = w->count;
 
@@ -780,26 +780,6 @@  static int wa_add(struct i915_workarounds *w,
 	return 0;
 }
 
-#define WA_REG(addr, mask, val) do { \
-		const int r = wa_add(&dev_priv->lri_workarounds, \
-				     (addr), (mask), (val)); \
-		WARN_ON(r); \
-	} while (0)
-
-#define WA_SET_BIT_MASKED(addr, mask) \
-	WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
-
-#define WA_CLR_BIT_MASKED(addr, mask) \
-	WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
-
-#define WA_SET_FIELD_MASKED(addr, mask, value) \
-	WA_REG(addr, mask, _MASKED_FIELD(mask, value))
-
-#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
-#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
-
-#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
-
 static int gen8_init_workarounds(struct intel_engine_cs *ring)
 {
 	struct drm_device *dev = ring->dev;