From patchwork Tue Oct 6 14:26:45 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 7335041 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2F772C0021 for ; Tue, 6 Oct 2015 14:27:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 526272071A for ; Tue, 6 Oct 2015 14:27:03 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id EDAEB206F3 for ; Tue, 6 Oct 2015 14:26:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6A52F6E104; Tue, 6 Oct 2015 07:26:58 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 86D946E176 for ; Tue, 6 Oct 2015 07:26:57 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP; 06 Oct 2015 07:26:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,644,1437462000"; d="scan'208";a="804789808" Received: from rosetta.fi.intel.com (HELO rosetta) ([10.237.72.50]) by fmsmga001.fm.intel.com with ESMTP; 06 Oct 2015 07:26:56 -0700 Received: by rosetta (Postfix, from userid 1000) id 035EF80090; Tue, 6 Oct 2015 17:26:56 +0300 (EEST) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2015 17:26:45 +0300 Message-Id: <1444141613-11152-5-git-send-email-mika.kuoppala@intel.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1444141613-11152-1-git-send-email-mika.kuoppala@intel.com> References: <1444141613-11152-1-git-send-email-mika.kuoppala@intel.com> Cc: miku@iki.fi Subject: [Intel-gfx] [PATCH 04/12] drm/i915: Move workaround macros to i915_drv.h X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The plan is to allow workaround list usage outside of intel_ringbuffer.c, mainly in intel_pm.c where we setup assortment of workaround registers as part of intel_init_clock_gating(). Move macros to i915_drv.h and export intel_wa_add(). Remove WA_WRITE macro as there are no users of it as of now. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_drv.h | 22 ++++++++++++++++++++++ drivers/gpu/drm/i915/intel_ringbuffer.c | 24 ++---------------------- 2 files changed, 24 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 1883847..5a04948 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3518,4 +3518,26 @@ static inline void i915_trace_irq_get(struct intel_engine_cs *ring, i915_gem_request_assign(&ring->trace_irq_req, req); } +/* Workaround register lists */ +#define WA_REG(addr, mask, val) do { \ + const int r = intel_wa_add(&dev_priv->lri_workarounds, \ + (addr), (mask), (val)); \ + WARN_ON(r); \ + } while (0) + +#define WA_SET_BIT_MASKED(addr, mask) \ + WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) + +#define WA_CLR_BIT_MASKED(addr, mask) \ + WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) + +#define WA_SET_FIELD_MASKED(addr, mask, value) \ + WA_REG(addr, mask, _MASKED_FIELD(mask, value)) + +#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ((addr)) | (mask)) +#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ((addr)) & ~(mask)) + +int intel_wa_add(struct i915_workarounds *w, + const u32 addr, const u32 mask, const u32 val); + #endif diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index bc8a8e2..29ae97e 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -763,8 +763,8 @@ static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) return ret; } -static int wa_add(struct i915_workarounds *w, - const u32 addr, const u32 mask, const u32 val) +int intel_wa_add(struct i915_workarounds *w, + const u32 addr, const u32 mask, const u32 val) { const u32 idx = w->count; @@ -780,26 +780,6 @@ static int wa_add(struct i915_workarounds *w, return 0; } -#define WA_REG(addr, mask, val) do { \ - const int r = wa_add(&dev_priv->lri_workarounds, \ - (addr), (mask), (val)); \ - WARN_ON(r); \ - } while (0) - -#define WA_SET_BIT_MASKED(addr, mask) \ - WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) - -#define WA_CLR_BIT_MASKED(addr, mask) \ - WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) - -#define WA_SET_FIELD_MASKED(addr, mask, value) \ - WA_REG(addr, mask, _MASKED_FIELD(mask, value)) - -#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) -#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) - -#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) - static int gen8_init_workarounds(struct intel_engine_cs *ring) { struct drm_device *dev = ring->dev;