From patchwork Tue Oct 6 14:26:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 7335081 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DBB70BF90C for ; Tue, 6 Oct 2015 14:27:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E2B3B20701 for ; Tue, 6 Oct 2015 14:27:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E0FB4206F9 for ; Tue, 6 Oct 2015 14:27:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D056C6E3F4; Tue, 6 Oct 2015 07:27:02 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 6544D6E3E2 for ; Tue, 6 Oct 2015 07:27:00 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP; 06 Oct 2015 07:27:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,644,1437462000"; d="scan'208";a="820532227" Received: from rosetta.fi.intel.com (HELO rosetta) ([10.237.72.50]) by orsmga002.jf.intel.com with ESMTP; 06 Oct 2015 07:26:59 -0700 Received: by rosetta (Postfix, from userid 1000) id 0A98780094; Tue, 6 Oct 2015 17:26:56 +0300 (EEST) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2015 17:26:49 +0300 Message-Id: <1444141613-11152-9-git-send-email-mika.kuoppala@intel.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1444141613-11152-1-git-send-email-mika.kuoppala@intel.com> References: <1444141613-11152-1-git-send-email-mika.kuoppala@intel.com> Cc: miku@iki.fi Subject: [Intel-gfx] [PATCH 08/12] drm/i915: Use mmio workaround list for skl/bxt X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some registers are, naturally, lost in gpu reset/suspend cycle. And some registers, for example in display domain and are not subject to gpu reset so they retain their contents. As hang recovery triggers a reset, recoverable gpu hang can currently flush out essential workarounds and cause havoc later on. When register GEN8_GARBNTL is missing the WaEnableGapsTsvCreditFix:skl, it can cause random system hangs [1]. This workaround was added in: commit 245d96670d26 ("drm/i915:skl: Add WaEnableGapsTsvCreditFix"). But another set of system hangs were observed and the failure pattern indicated that there was random gpu hang preceding the system hang [2]. This lead to the realization that we lose this workaround and BDW_SCRATCH1 on reset. Add workarounds in skl/bxt init clock gating path to mmio workaround list. This exposes these registers to the same testing mechanism in use with the lri workarounds, gem_workarounds. References: [1] https://bugs.freedesktop.org/show_bug.cgi?id=90854 References: https://bugs.freedesktop.org/show_bug.cgi?id=92315 Testcase: igt/gem_workarounds Reported-by: Tomi Sarvela Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_pm.c | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e97f271..61136e1 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -73,12 +73,11 @@ static void gen9_init_clock_gating(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; /* WaEnableLbsSlaRetryTimerDecrement:skl */ - I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | + WA_SET_BIT(MMIO, BDW_SCRATCH1, GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); /* WaDisableKillLogic:bxt,skl */ - I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | - ECOCHK_DIS_TLB); + WA_SET_BIT(MMIO, GAM_ECOCHK, ECOCHK_DIS_TLB); } static void skl_init_clock_gating(struct drm_device *dev) @@ -89,12 +88,11 @@ static void skl_init_clock_gating(struct drm_device *dev) if (INTEL_REVID(dev) <= SKL_REVID_D0) { /* WaDisableHDCInvalidation:skl */ - I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | - BDW_DISABLE_HDC_INVALIDATION); + WA_SET_BIT(MMIO, GAM_ECOCHK, BDW_DISABLE_HDC_INVALIDATION); /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ - I915_WRITE(FF_SLICE_CS_CHICKEN2, - _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); + WA_SET_BIT_MASKED(MMIO, FF_SLICE_CS_CHICKEN2, + GEN9_TSG_BARRIER_ACK_DISABLE); } /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes @@ -102,13 +100,12 @@ static void skl_init_clock_gating(struct drm_device *dev) */ if (INTEL_REVID(dev) <= SKL_REVID_E0) /* WaDisableLSQCROPERFforOCL:skl */ - I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | - GEN8_LQSC_RO_PERF_DIS); + WA_SET_BIT(MMIO, GEN8_L3SQCREG4, GEN8_LQSC_RO_PERF_DIS); /* WaEnableGapsTsvCreditFix:skl */ if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) { - I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | - GEN9_GAPS_TSV_CREDIT_DISABLE)); + WA_SET_BIT(MMIO, GEN8_GARBCNTL, + GEN9_GAPS_TSV_CREDIT_DISABLE); } } @@ -119,25 +116,23 @@ static void bxt_init_clock_gating(struct drm_device *dev) gen9_init_clock_gating(dev); /* WaDisableSDEUnitClockGating:bxt */ - I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | - GEN8_SDEUNIT_CLOCK_GATE_DISABLE); + WA_SET_BIT(MMIO, GEN8_UCGCTL6, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); /* * FIXME: * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. */ - I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | - GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); + WA_SET_BIT(MMIO, GEN8_UCGCTL6, GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); /* WaStoreMultiplePTEenable:bxt */ /* This is a requirement according to Hardware specification */ if (INTEL_REVID(dev) == BXT_REVID_A0) - I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); + WA_SET_BIT(MMIO, TILECTL, TILECTL_TLBPF); /* WaSetClckGatingDisableMedia:bxt */ if (INTEL_REVID(dev) == BXT_REVID_A0) { - I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & - ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); + WA_CLR_BIT(MMIO, GEN7_MISCCPCTL, + GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE); } }