From patchwork Wed Oct 7 11:44:00 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Jerez X-Patchwork-Id: 7344611 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1FB459F302 for ; Wed, 7 Oct 2015 11:41:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1AFE5206DE for ; Wed, 7 Oct 2015 11:41:44 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E3CC22069B for ; Wed, 7 Oct 2015 11:41:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CD2AD6E950; Wed, 7 Oct 2015 04:41:41 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) by gabe.freedesktop.org (Postfix) with ESMTPS id F20186E950 for ; Wed, 7 Oct 2015 04:41:39 -0700 (PDT) Received: from piha.riseup.net (unknown [10.0.1.162]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (Client CN "*.riseup.net", Issuer "COMODO RSA Domain Validation Secure Server CA" (verified OK)) by mx1.riseup.net (Postfix) with ESMTPS id 439C2C2906; Wed, 7 Oct 2015 04:41:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1444218099; bh=BN+6tDkVet5NklZ3zS8Sb7b9uPmkhMbqfRDAAp+1xE8=; h=From:To:Cc:Subject:Date:From; b=ZGmAOzOUjqM+qzf+ubbISYhFRkVlnKVMtWYdIOCZKVwF53TnA4H0onhlBUP60X7yQ ozmR0sUrm5UVfU/zmllGNA8w0mwoMGPhiySSpXPh/Q/wgJU1nXvBFanv+JtaY+FMNt evZBJkXENc0U8xL0UH+dr3xE8F7MH1dMsFtrCJnU= Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: currojerez) with ESMTPSA id 46D2B1404B3 From: Francisco Jerez To: intel-gfx@lists.freedesktop.org Date: Wed, 7 Oct 2015 14:44:00 +0300 Message-Id: <1444218245-8430-1-git-send-email-currojerez@riseup.net> X-Mailer: git-send-email 2.5.1 X-Virus-Scanned: clamav-milter 0.98.7 at mx1.riseup.net X-Virus-Status: Clean Subject: [Intel-gfx] [PATCH 1/6] drm/i915: Implement L3 partitioning set-up from the workaround list. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This programs the L3 configuration based on the sizes given for each partition as arguments. The relevant register writes are added to the workaround list so that they are re-applied to each context while it's initialized, preventing state leaks from other userspace processes which may have modified the L3 partitioning from its boot-up state, since all relevant registers are part of the software and hardware command checker whitelists. Some userspace clients (DDX and current versions of Mesa not patched with my L3 partitioning series [1]) assume that the L3 configuration, in particular the URB size, comes up in certain state when a context is created, but nothing in the kernel guarantees this assumption, the registers that control the partitioning of the L3 cache were being left untouched. Note that the VLV_L3SQCREG1_SQGHPCI_DEFAULT macro defined here has the same value as the previously defined VLV_B0_WA_L3SQCREG1_VALUE, but the latter will be removed in a future commit. [1] http://lists.freedesktop.org/archives/mesa-dev/2015-September/093550.html Signed-off-by: Francisco Jerez --- drivers/gpu/drm/i915/i915_reg.h | 13 ++++++ drivers/gpu/drm/i915/intel_ringbuffer.c | 80 +++++++++++++++++++++++++++++++++ 2 files changed, 93 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a7c9e8c..663bc8f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5920,11 +5920,21 @@ enum skl_disp_power_wells { # define CHV_HZ_8X8_MODE_IN_1X (1<<15) # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3) +#define GEN8_L3CNTLREG 0x7034 +#define GEN8_L3CNTLREG_URB_ALLOC(n) ((n) << 1) +#define GEN8_L3CNTLREG_RO_ALLOC(n) ((n) << 11) +#define GEN8_L3CNTLREG_DC_ALLOC(n) ((n) << 18) +#define GEN8_L3CNTLREG_ALL_ALLOC(n) ((n) << 25) + #define GEN9_SLICE_COMMON_ECO_CHICKEN0 0x7308 #define DISABLE_PIXEL_MASK_CAMMING (1<<14) #define GEN7_L3SQCREG1 0xB010 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 +#define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000 +#define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00D30000 +#define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000 +#define GEN7_L3SQCREG1_CONV_DC_UC (1 << 24) #define GEN8_L3SQCREG1 0xB100 #define BDW_WA_L3SQCREG1_DEFAULT 0x784000 @@ -5933,6 +5943,9 @@ enum skl_disp_power_wells { #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C #define GEN7_L3AGDIS (1<<19) #define GEN7_L3CNTLREG2 0xB020 +#define GEN7_L3CNTLREG2_URB_ALLOC(n) ((n) << 1) +#define GEN7_L3CNTLREG2_RO_ALLOC(n) ((n) << 14) +#define GEN7_L3CNTLREG2_DC_ALLOC(n) ((n) << 21) #define GEN7_L3CNTLREG3 0xB024 #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 9035f8c..54ca344 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -800,6 +800,86 @@ static int wa_add(struct drm_i915_private *dev_priv, #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) +/** + * init_l3_partitioning_workarounds - Add L3 partitioning set-up to the WA list. + * + * @ring - Ring to program the L3 partitioning for. + * @n_urb - Number of ways to allocate for the URB. + * @n_ro - Number of ways to allocate for read-only L3 clients. + * @n_dc - Number of ways to allocate for the DC read-write L3 client. + * @n_all - Number of ways to allocate for the common pool shared + * among all L3 clients. + * + * Note that for this to work correctly the L3 cache must be + * completely flushed whenever the workaround list is applied to a + * context. + */ +static int init_l3_partitioning_workarounds(struct intel_engine_cs *ring, + unsigned int n_urb, + unsigned int n_ro, + unsigned int n_dc, + unsigned int n_all) +{ + struct drm_device *dev = ring->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + + if (INTEL_INFO(dev)->gen >= 8) { + /* + * The ALL partition may not be used simultaneously + * with RO and DC. + */ + BUG_ON(n_all && (n_ro || n_dc)); + + /* Just need to set up the L3 partitioning. */ + WA_WRITE(GEN8_L3CNTLREG, + GEN8_L3CNTLREG_URB_ALLOC(n_urb) | + GEN8_L3CNTLREG_RO_ALLOC(n_ro) | + GEN8_L3CNTLREG_DC_ALLOC(n_dc) | + GEN8_L3CNTLREG_ALL_ALLOC(n_all)); + + } else if (INTEL_INFO(dev)->gen >= 7) { + /* + * Offset applied by the hardware to the number of + * ways allocated to the URB, which is also the + * minimum legal URB allocation. + */ + const unsigned int n0_urb = (IS_VALLEYVIEW(dev) ? 32 : 0); + BUG_ON(n_urb < n0_urb); + + /* The ALL partition is not supported on Gen7. */ + BUG_ON(n_all); + + /* + * Init the L3SQ General and high priority credit + * initialization value to the hardware defaults + * (except for VLV B0 which supposedly defaults to a + * value different to the one we set here), and demote + * the DC to LLC if it has no ways assigned. + * + * WaIncreaseL3CreditsForVLVB0:vlv + */ + WA_WRITE(GEN7_L3SQCREG1, + (IS_HASWELL(dev) ? HSW_L3SQCREG1_SQGHPCI_DEFAULT : + IS_VALLEYVIEW(dev) ? VLV_L3SQCREG1_SQGHPCI_DEFAULT : + IVB_L3SQCREG1_SQGHPCI_DEFAULT) | + (n_dc ? 0 : GEN7_L3SQCREG1_CONV_DC_UC)); + + /* Set up the L3 partitioning. */ + WA_WRITE(GEN7_L3CNTLREG2, + GEN7_L3CNTLREG2_URB_ALLOC(n_urb - n0_urb) | + GEN7_L3CNTLREG2_RO_ALLOC(n_ro) | + GEN7_L3CNTLREG2_DC_ALLOC(n_dc)); + + WA_WRITE(GEN7_L3CNTLREG3, 0); + + } else { + /* No L3 on pre-Gen7 hardware. */ + BUG(); + } + + return 0; +} + static int gen8_init_workarounds(struct intel_engine_cs *ring) { struct drm_device *dev = ring->dev;