From patchwork Wed Oct 7 11:44:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Jerez X-Patchwork-Id: 7344641 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id DD5839F302 for ; Wed, 7 Oct 2015 11:41:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 09ECC206AD for ; Wed, 7 Oct 2015 11:41:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 0FE9220741 for ; Wed, 7 Oct 2015 11:41:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 77BC96EAFE; Wed, 7 Oct 2015 04:41:44 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8C9C16EB4F for ; Wed, 7 Oct 2015 04:41:43 -0700 (PDT) Received: from piha.riseup.net (unknown [10.0.1.162]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (Client CN "*.riseup.net", Issuer "COMODO RSA Domain Validation Secure Server CA" (verified OK)) by mx1.riseup.net (Postfix) with ESMTPS id 61DDCC0F25; Wed, 7 Oct 2015 04:41:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1444218103; bh=WDECIkxMaNzRaHvvBeC76NYvmcn8y0un+ewBXuu+wh4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=j13F5N5+VaAmxMMo8Sujh0sfj1ae+7KN7G7Cfperinngw3yARaYsTU65QOCkKQBBE iim6BqaWejWVTzM/NEdINaYo8wM5f5x+SGcLhDqYV6RmSIvslb7aLqncmcfGgSuH42 6IG3z50R0gglAOfoqwOt3GIR1FwcmuGrvdIlvWPw= Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: currojerez) with ESMTPSA id 809C41404B3 From: Francisco Jerez To: intel-gfx@lists.freedesktop.org Date: Wed, 7 Oct 2015 14:44:03 +0300 Message-Id: <1444218245-8430-4-git-send-email-currojerez@riseup.net> X-Mailer: git-send-email 2.5.1 In-Reply-To: <1444218245-8430-1-git-send-email-currojerez@riseup.net> References: <1444218245-8430-1-git-send-email-currojerez@riseup.net> X-Virus-Scanned: clamav-milter 0.98.7 at mx1.riseup.net X-Virus-Status: Clean Subject: [Intel-gfx] [PATCH 4/6] drm/i915: Program the L3 configuration to hardware defaults on context init. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use init_l3_partitioning_workarounds() to set up the L3 partitioning on context creation according to the hardware boot-up defaults for each device. Signed-off-by: Francisco Jerez --- drivers/gpu/drm/i915/intel_ringbuffer.c | 53 +++++++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index e2e40d0..c4c39c4 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -880,6 +880,36 @@ static int init_l3_partitioning_workarounds(struct intel_engine_cs *ring, return 0; } +static int ivb_init_workarounds(struct intel_engine_cs *ring) +{ + /* + * Set up the default L3 partitioning of the hardware of 32 + * ways (i.e. 256 KB on GT2 parts) for the URB and another 32 + * ways for the RO partition. + */ + return init_l3_partitioning_workarounds(ring, 32, 32, 0, 0); +} + +static int vlv_init_workarounds(struct intel_engine_cs *ring) +{ + /* + * Set up the default L3 partitioning of the hardware of 64 + * ways (i.e. 128 KB) for the URB, 16 ways (i.e. 32 KB) for + * the RO partition and another 16 ways for the DC. + */ + return init_l3_partitioning_workarounds(ring, 64, 16, 16, 0); +} + +static int hsw_init_workarounds(struct intel_engine_cs *ring) +{ + /* + * Set up the default L3 partitioning of the hardware of 32 + * ways (i.e. 256 KB on GT2 parts) for the URB and another 32 + * ways for the RO partition. + */ + return init_l3_partitioning_workarounds(ring, 32, 32, 0, 0); +} + static int gen8_init_workarounds(struct intel_engine_cs *ring) { struct drm_device *dev = ring->dev; @@ -929,7 +959,12 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring) GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4); - return 0; + /* + * Set up the default L3 partitioning of the hardware of 48 + * ways (i.e. 384 KB on GT2 parts, 192 KB on GT1 parts and + * CHV) for the URB and another 48 ways for the RO partition. + */ + return init_l3_partitioning_workarounds(ring, 48, 0, 0, 48); } static int bdw_init_workarounds(struct intel_engine_cs *ring) @@ -1053,7 +1088,12 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) /* WaDisableSTUnitPowerOptimization:skl,bxt */ WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); - return 0; + /* + * Set up the default L3 partitioning of the hardware of 48 + * ways (i.e. 384 KB on GT2 parts, 192 KB on GT1 parts and + * BXT) for the URB and another 48 ways for the RO partition. + */ + return init_l3_partitioning_workarounds(ring, 48, 0, 0, 48); } static int skl_tune_iz_hashing(struct intel_engine_cs *ring) @@ -1175,6 +1215,15 @@ int init_workarounds_ring(struct intel_engine_cs *ring) dev_priv->workarounds.count = 0; + if (IS_IVYBRIDGE(dev)) + return ivb_init_workarounds(ring); + + if (IS_VALLEYVIEW(dev)) + return vlv_init_workarounds(ring); + + if (IS_HASWELL(dev)) + return hsw_init_workarounds(ring); + if (IS_BROADWELL(dev)) return bdw_init_workarounds(ring);