From patchwork Wed Oct 7 11:44:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Jerez X-Patchwork-Id: 7344651 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C308E9F444 for ; Wed, 7 Oct 2015 11:41:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F1FC72069B for ; Wed, 7 Oct 2015 11:41:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 304B3206DE for ; Wed, 7 Oct 2015 11:41:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 94B976EB33; Wed, 7 Oct 2015 04:41:45 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) by gabe.freedesktop.org (Postfix) with ESMTPS id B57A56EB33 for ; Wed, 7 Oct 2015 04:41:44 -0700 (PDT) Received: from piha.riseup.net (unknown [10.0.1.162]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (Client CN "*.riseup.net", Issuer "COMODO RSA Domain Validation Secure Server CA" (verified OK)) by mx1.riseup.net (Postfix) with ESMTPS id 907CFC1554; Wed, 7 Oct 2015 04:41:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1444218104; bh=+goGmx7vzrTbaq75CrVoLg4ctpM/MmBOZ+pidEbVZlQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Z0qqkJ4lDCK45w14dEqK2PKGK07cfjMSl/CyGh9sCQN/EVEu5nZrxlhH4pwDkoSSU 2a3tAwuVg2dBDkEnOQO3n0GW3CZA9gclq+2TeQOwlGD4HZFtRUuhuISKdbvyJzOSSi +fJSZoALzCRQWJiOEQWSbxX8aRcLLuErhIVLVX1s= Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: currojerez) with ESMTPSA id C46B51404B3 From: Francisco Jerez To: intel-gfx@lists.freedesktop.org Date: Wed, 7 Oct 2015 14:44:04 +0300 Message-Id: <1444218245-8430-5-git-send-email-currojerez@riseup.net> X-Mailer: git-send-email 2.5.1 In-Reply-To: <1444218245-8430-1-git-send-email-currojerez@riseup.net> References: <1444218245-8430-1-git-send-email-currojerez@riseup.net> X-Virus-Scanned: clamav-milter 0.98.7 at mx1.riseup.net X-Virus-Status: Clean Subject: [Intel-gfx] [PATCH 5/6] drm/i915/hsw: Move L3 atomics workaround to the workaround list. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This makes sure that the workaround is not accidentally undone by some process (which is possible because the HSW_SCRATCH1 and HSW_ROW_CHICKEN3 registers are partially whitelisted), what could cause the next context to be created to hang if it wasn't expecting L3 atomics to be enabled. Signed-off-by: Francisco Jerez --- drivers/gpu/drm/i915/intel_pm.c | 5 ----- drivers/gpu/drm/i915/intel_ringbuffer.c | 12 ++++++++++++ 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 60d120c..d495043 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6585,11 +6585,6 @@ static void haswell_init_clock_gating(struct drm_device *dev) ilk_init_lp_watermarks(dev); - /* L3 caching of data atomics doesn't work -- disable it. */ - I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); - I915_WRITE(HSW_ROW_CHICKEN3, - _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); - /* This is required by WaCatErrorRejectionIssue:hsw */ I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index c4c39c4..4cb9f5c 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -902,6 +902,18 @@ static int vlv_init_workarounds(struct intel_engine_cs *ring) static int hsw_init_workarounds(struct intel_engine_cs *ring) { + struct drm_i915_private *dev_priv = ring->dev->dev_private; + + /* + * L3 caching of data atomics can easily cause a full-system + * hang if not used with extreme care -- Disable it on all + * contexts by default, userspace is free to re-enable them if + * it knows what it's doing. + */ + WA_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); + WA_WRITE(HSW_ROW_CHICKEN3, + _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); + /* * Set up the default L3 partitioning of the hardware of 32 * ways (i.e. 256 KB on GT2 parts) for the URB and another 32