From patchwork Wed Oct 7 11:44:05 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Jerez X-Patchwork-Id: 7344661 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8F7ABBEEA4 for ; Wed, 7 Oct 2015 11:41:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C1CC0206AD for ; Wed, 7 Oct 2015 11:41:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id DA0092069B for ; Wed, 7 Oct 2015 11:41:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5226C6EB37; Wed, 7 Oct 2015 04:41:47 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0E1016EB4F for ; Wed, 7 Oct 2015 04:41:46 -0700 (PDT) Received: from piha.riseup.net (unknown [10.0.1.162]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (Client CN "*.riseup.net", Issuer "COMODO RSA Domain Validation Secure Server CA" (verified OK)) by mx1.riseup.net (Postfix) with ESMTPS id CE6B9C267E; Wed, 7 Oct 2015 04:41:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1444218105; bh=xj0wB7CIcTSKwCunaX0Wd5Z+arUNDGo6nZ1+ImsojHk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PFj0idGE/pAZAE36y7jco1tjeMoChgs5BuJDAu1FUidCQetjDsGLDZXyj2tWQ1x4I bN4L1s7PC/gNtWOUeeljnp223RXhG8TaaajhM2QWdfcMZg98WGVzHwb+6ccFwObo/0 rEQxkMQB8GNBqhNbj8sU5DLIFlzmufhFwDy8n4eQ= Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: currojerez) with ESMTPSA id F36851404B3 From: Francisco Jerez To: intel-gfx@lists.freedesktop.org Date: Wed, 7 Oct 2015 14:44:05 +0300 Message-Id: <1444218245-8430-6-git-send-email-currojerez@riseup.net> X-Mailer: git-send-email 2.5.1 In-Reply-To: <1444218245-8430-1-git-send-email-currojerez@riseup.net> References: <1444218245-8430-1-git-send-email-currojerez@riseup.net> X-Virus-Scanned: clamav-milter 0.98.7 at mx1.riseup.net X-Virus-Status: Clean Subject: [Intel-gfx] [PATCH 6/6] drm/i915/vlv: Remove WaIncreaseL3CreditsForVLVB0 from init_clock_gating. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The same work-arond is applied per-context in init_l3_partitioning_workarounds(), so the direct MMIO write of GEN7_L3SQCREG1 should be redundant now. Applying the work-around at context creation time also makes sure that the MMIO writes are not accidentally undone by userspace. Signed-off-by: Francisco Jerez --- drivers/gpu/drm/i915/i915_reg.h | 1 - drivers/gpu/drm/i915/intel_pm.c | 6 ------ 2 files changed, 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 663bc8f..b445c93 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5930,7 +5930,6 @@ enum skl_disp_power_wells { #define DISABLE_PIXEL_MASK_CAMMING (1<<14) #define GEN7_L3SQCREG1 0xB010 -#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00D30000 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d495043..ccb91d3 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6810,12 +6810,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev) _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); /* - * WaIncreaseL3CreditsForVLVB0:vlv - * This is the hardware default actually. - */ - I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); - - /* * WaDisableVLVClockGating_VBIIssue:vlv * Disable clock gating on th GCFG unit to prevent a delay * in the reporting of vblank events.