Message ID | 1444840154-7804-19-git-send-email-ville.syrjala@linux.intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On Wed, Oct 14, 2015 at 07:29:10PM +0300, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > We convert the fb->offsets[] into x/y offsets, so they must be > (macro)pixel aligned. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 36 +++++++++++++++++++++++++++++++++--- > 1 file changed, 33 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index ce346cfe..70e6e27 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -14284,6 +14284,36 @@ u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, > } > } > > +static int intel_fb_check_offsets(const struct drm_mode_fb_cmd2 *mode_cmd) > +{ > + uint32_t format = mode_cmd->pixel_format; > + int i; > + > + for (i = 0; i < drm_format_num_planes(format); i++) { > + unsigned int cpp; > + > + switch (format) { > + case DRM_FORMAT_YUYV: > + case DRM_FORMAT_UYVY: > + case DRM_FORMAT_YVYU: > + case DRM_FORMAT_VYUY: > + cpp = 4; > + break; > + default: > + cpp = drm_format_plane_cpp(format, i); > + break; Might be worth it to extract this into a drm helper. gallium also has the concept of a pixel block size, and it's _really_ nice imo. -Daniel > + } > + > + if (mode_cmd->offsets[i] % cpp) { > + DRM_DEBUG("fb plane %d offset 0x%08x not (macro)pixel aligned\n", > + i, mode_cmd->offsets[i]); > + return -EINVAL; > + } > + } > + > + return 0; > +} > + > static int intel_framebuffer_init(struct drm_device *dev, > struct intel_framebuffer *intel_fb, > struct drm_mode_fb_cmd2 *mode_cmd, > @@ -14410,9 +14440,9 @@ static int intel_framebuffer_init(struct drm_device *dev, > return -EINVAL; > } > > - /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ > - if (mode_cmd->offsets[0] != 0) > - return -EINVAL; > + ret = intel_fb_check_offsets(mode_cmd); > + if (ret) > + return ret; > > aligned_height = intel_fb_align_height(dev, mode_cmd->height, > mode_cmd->pixel_format, > -- > 2.4.9 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Wed, Oct 14, 2015 at 07:29:10PM +0300, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > We convert the fb->offsets[] into x/y offsets, so they must be > (macro)pixel aligned. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Patches 16-18: Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> > --- > drivers/gpu/drm/i915/intel_display.c | 36 +++++++++++++++++++++++++++++++++--- > 1 file changed, 33 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index ce346cfe..70e6e27 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -14284,6 +14284,36 @@ u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, > } > } > > +static int intel_fb_check_offsets(const struct drm_mode_fb_cmd2 *mode_cmd) > +{ > + uint32_t format = mode_cmd->pixel_format; > + int i; > + > + for (i = 0; i < drm_format_num_planes(format); i++) { > + unsigned int cpp; > + > + switch (format) { > + case DRM_FORMAT_YUYV: > + case DRM_FORMAT_UYVY: > + case DRM_FORMAT_YVYU: > + case DRM_FORMAT_VYUY: > + cpp = 4; > + break; > + default: > + cpp = drm_format_plane_cpp(format, i); > + break; > + } > + > + if (mode_cmd->offsets[i] % cpp) { > + DRM_DEBUG("fb plane %d offset 0x%08x not (macro)pixel aligned\n", > + i, mode_cmd->offsets[i]); > + return -EINVAL; > + } > + } > + > + return 0; > +} > + > static int intel_framebuffer_init(struct drm_device *dev, > struct intel_framebuffer *intel_fb, > struct drm_mode_fb_cmd2 *mode_cmd, > @@ -14410,9 +14440,9 @@ static int intel_framebuffer_init(struct drm_device *dev, > return -EINVAL; > } > > - /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ > - if (mode_cmd->offsets[0] != 0) > - return -EINVAL; > + ret = intel_fb_check_offsets(mode_cmd); > + if (ret) > + return ret; > > aligned_height = intel_fb_align_height(dev, mode_cmd->height, > mode_cmd->pixel_format, > -- > 2.4.9 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ce346cfe..70e6e27 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -14284,6 +14284,36 @@ u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, } } +static int intel_fb_check_offsets(const struct drm_mode_fb_cmd2 *mode_cmd) +{ + uint32_t format = mode_cmd->pixel_format; + int i; + + for (i = 0; i < drm_format_num_planes(format); i++) { + unsigned int cpp; + + switch (format) { + case DRM_FORMAT_YUYV: + case DRM_FORMAT_UYVY: + case DRM_FORMAT_YVYU: + case DRM_FORMAT_VYUY: + cpp = 4; + break; + default: + cpp = drm_format_plane_cpp(format, i); + break; + } + + if (mode_cmd->offsets[i] % cpp) { + DRM_DEBUG("fb plane %d offset 0x%08x not (macro)pixel aligned\n", + i, mode_cmd->offsets[i]); + return -EINVAL; + } + } + + return 0; +} + static int intel_framebuffer_init(struct drm_device *dev, struct intel_framebuffer *intel_fb, struct drm_mode_fb_cmd2 *mode_cmd, @@ -14410,9 +14440,9 @@ static int intel_framebuffer_init(struct drm_device *dev, return -EINVAL; } - /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ - if (mode_cmd->offsets[0] != 0) - return -EINVAL; + ret = intel_fb_check_offsets(mode_cmd); + if (ret) + return ret; aligned_height = intel_fb_align_height(dev, mode_cmd->height, mode_cmd->pixel_format,