From patchwork Thu Oct 15 13:22:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vandana.kannan@intel.com X-Patchwork-Id: 7405891 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 12E899F302 for ; Thu, 15 Oct 2015 12:55:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 30BD32083F for ; Thu, 15 Oct 2015 12:55:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 4131120836 for ; Thu, 15 Oct 2015 12:55:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A102E6EE79; Thu, 15 Oct 2015 05:55:03 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id A9D996EE79 for ; Thu, 15 Oct 2015 05:55:01 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP; 15 Oct 2015 05:55:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,685,1437462000"; d="scan'208";a="827345692" Received: from vkannan-desktop.iind.intel.com ([10.223.25.49]) by orsmga002.jf.intel.com with ESMTP; 15 Oct 2015 05:55:01 -0700 From: Vandana Kannan To: intel-gfx@lists.freedesktop.org Date: Thu, 15 Oct 2015 18:52:49 +0530 Message-Id: <1444915369-32134-3-git-send-email-vandana.kannan@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1444915369-32134-1-git-send-email-vandana.kannan@intel.com> References: <1444915369-32134-1-git-send-email-vandana.kannan@intel.com> Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Add crtc_clock_get for hsw, skl, bxt X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Reusing the ddi_clock_get functions for hsw, skl, bxt and creating a common crtc_clock_get function. for BXT, there is a difference in clock between DSI and DDI. Taking care of this as well. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_display.c | 43 +++++++++++++++++++++++++++++++++--- 1 file changed, 40 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d98385e..c9fcadd 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -34,6 +34,7 @@ #include #include #include "intel_drv.h" +#include "intel_dsi.h" #include #include "i915_drv.h" #include "i915_trace.h" @@ -112,6 +113,15 @@ static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_cr struct intel_crtc_state *crtc_state); static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, int num_connectors); +static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, + enum port port, + struct intel_crtc_state *pipe_config); +static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, + enum port port, + struct intel_crtc_state *pipe_config); +static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, + enum port port, + struct intel_crtc_state *pipe_config); static void skylake_pfit_enable(struct intel_crtc *crtc); static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); static void ironlake_pfit_enable(struct intel_crtc *crtc); @@ -8050,6 +8060,33 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc, pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); } +static void haswell_crtc_clock_get(struct intel_crtc *crtc, + struct intel_crtc_state *pipe_config) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_encoder *encoder = NULL; + enum port port; + bool is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); + + for_each_encoder_on_crtc(dev, &crtc->base, encoder) { + port = intel_ddi_get_encoder_port(encoder); + if (IS_BROXTON(dev) && is_dsi) { + pipe_config->port_clock = bxt_get_dsi_pclk(encoder, + pipe_config->pipe_bpp); + break; + } + if (IS_SKYLAKE(dev)) + skylake_get_ddi_pll(dev_priv, port, pipe_config); + else if (IS_BROXTON(dev)) + bxt_get_ddi_pll(dev_priv, port, pipe_config); + else + haswell_get_ddi_pll(dev_priv, port, pipe_config); + + intel_ddi_clock_get(encoder, pipe_config); + } +} + static bool i9xx_get_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { @@ -10577,7 +10614,7 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = dev->dev_private; /* read out port_clock from the DPLL */ - dev_priv->display.crtc_clock_get(crtc, &pipe_config); + dev_priv->display.crtc_clock_get(crtc, pipe_config); /* * This value does not include pixel_multiplier. @@ -14409,7 +14446,7 @@ static void intel_init_display(struct drm_device *dev) dev_priv->display.crtc_disable = haswell_crtc_disable; dev_priv->display.update_primary_plane = skylake_update_primary_plane; - dev_priv->display.crtc_clock_get = i9xx_crtc_clock_get; + dev_priv->display.crtc_clock_get = haswell_crtc_clock_get; } else if (HAS_DDI(dev)) { dev_priv->display.get_pipe_config = haswell_get_pipe_config; dev_priv->display.get_initial_plane_config = @@ -14420,7 +14457,7 @@ static void intel_init_display(struct drm_device *dev) dev_priv->display.crtc_disable = haswell_crtc_disable; dev_priv->display.update_primary_plane = ironlake_update_primary_plane; - dev_priv->display.crtc_clock_get = i9xx_crtc_clock_get; + dev_priv->display.crtc_clock_get = haswell_crtc_clock_get; } else if (HAS_PCH_SPLIT(dev)) { dev_priv->display.get_pipe_config = ironlake_get_pipe_config; dev_priv->display.get_initial_plane_config =