@@ -368,7 +368,6 @@ static int execlists_update_context(struct drm_i915_gem_request *rq)
WARN_ON(!i915_gem_obj_is_pinned(rb_obj));
reg_state[CTX_RING_TAIL+1] = rq->tail;
- reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj);
if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
/* True 32b PPGTT with dynamic page allocation: update PDP
@@ -1027,6 +1026,9 @@ static int intel_lr_context_do_pin(
if (ret)
goto unpin_rb_obj;
+ ctx->engine[ring->id].reg_state[CTX_RING_BUFFER_START+1] =
+ i915_gem_obj_ggtt_offset(ringbuf->obj);
+
ctx_obj->dirty = true;
/* Invalidate GuC TLB. */
We now only need to update the address of the ringbuf object in the hw context when it is pinned, and the hw context is first CPU mapped Issue: VIZ-4277 Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> Cc: David Gordon <david.s.gordon@intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)