diff mbox

[10/14] drm/i915: s/DP_PLL_FREQ_160MHZ/DP_PLL_FREQ_162MHZ/

Message ID 1446146763-31821-11-git-send-email-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä Oct. 29, 2015, 7:25 p.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The DP link frequency is 162MHz, not 160MHz. Rename the ILK eDP PLL
defines to match.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  2 +-
 drivers/gpu/drm/i915/intel_dp.c | 10 +++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

Comments

Daniel Vetter Oct. 30, 2015, 3:49 p.m. UTC | #1
On Thu, Oct 29, 2015 at 09:25:59PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The DP link frequency is 162MHz, not 160MHz. Rename the ILK eDP PLL
> defines to match.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

ocd ftw. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

> ---
>  drivers/gpu/drm/i915/i915_reg.h |  2 +-
>  drivers/gpu/drm/i915/intel_dp.c | 10 +++++-----
>  2 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8942532..d02e3c7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4199,7 +4199,7 @@ enum skl_disp_power_wells {
>  
>  /* eDP */
>  #define   DP_PLL_FREQ_270MHZ		(0 << 16)
> -#define   DP_PLL_FREQ_160MHZ		(1 << 16)
> +#define   DP_PLL_FREQ_162MHZ		(1 << 16)
>  #define   DP_PLL_FREQ_MASK		(3 << 16)
>  
>  /* locked once port is enabled */
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 0b9b440..55d5246 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1557,11 +1557,11 @@ static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
>  
>  	if (crtc->config->port_clock == 162000) {
>  		/* For a long time we've carried around a ILK-DevA w/a for the
> -		 * 160MHz clock. If we're really unlucky, it's still required.
> +		 * 162MHz clock. If we're really unlucky, it's still required.
>  		 */
> -		DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
> -		dpa_ctl |= DP_PLL_FREQ_160MHZ;
> -		intel_dp->DP |= DP_PLL_FREQ_160MHZ;
> +		DRM_DEBUG_KMS("162MHz cpu eDP clock, might need ilk devA w/a\n");
> +		dpa_ctl |= DP_PLL_FREQ_162MHZ;
> +		intel_dp->DP |= DP_PLL_FREQ_162MHZ;
>  	} else {
>  		dpa_ctl |= DP_PLL_FREQ_270MHZ;
>  		intel_dp->DP |= DP_PLL_FREQ_270MHZ;
> @@ -2324,7 +2324,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
>  	intel_dp_get_m_n(crtc, pipe_config);
>  
>  	if (port == PORT_A) {
> -		if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
> +		if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
>  			pipe_config->port_clock = 162000;
>  		else
>  			pipe_config->port_clock = 270000;
> -- 
> 2.4.10
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8942532..d02e3c7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4199,7 +4199,7 @@  enum skl_disp_power_wells {
 
 /* eDP */
 #define   DP_PLL_FREQ_270MHZ		(0 << 16)
-#define   DP_PLL_FREQ_160MHZ		(1 << 16)
+#define   DP_PLL_FREQ_162MHZ		(1 << 16)
 #define   DP_PLL_FREQ_MASK		(3 << 16)
 
 /* locked once port is enabled */
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0b9b440..55d5246 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1557,11 +1557,11 @@  static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 
 	if (crtc->config->port_clock == 162000) {
 		/* For a long time we've carried around a ILK-DevA w/a for the
-		 * 160MHz clock. If we're really unlucky, it's still required.
+		 * 162MHz clock. If we're really unlucky, it's still required.
 		 */
-		DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
-		dpa_ctl |= DP_PLL_FREQ_160MHZ;
-		intel_dp->DP |= DP_PLL_FREQ_160MHZ;
+		DRM_DEBUG_KMS("162MHz cpu eDP clock, might need ilk devA w/a\n");
+		dpa_ctl |= DP_PLL_FREQ_162MHZ;
+		intel_dp->DP |= DP_PLL_FREQ_162MHZ;
 	} else {
 		dpa_ctl |= DP_PLL_FREQ_270MHZ;
 		intel_dp->DP |= DP_PLL_FREQ_270MHZ;
@@ -2324,7 +2324,7 @@  static void intel_dp_get_config(struct intel_encoder *encoder,
 	intel_dp_get_m_n(crtc, pipe_config);
 
 	if (port == PORT_A) {
-		if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
+		if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
 			pipe_config->port_clock = 162000;
 		else
 			pipe_config->port_clock = 270000;