| Message ID | 1447776866-29384-1-git-send-email-mika.kuoppala@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Nov 17, 2015 at 06:14:26PM +0200, Mika Kuoppala wrote: > With gen < 9 we have had always 50Mhz units as our hw > ratio. With gen >= 9 the hw ratio changed to 16.667Mhz (50/3). > The result was that our gpu frequency tracing started to output > values 3 times larger than expected due to hardcoded scaling > value. Fix this by using Use intel_gpu_freq() when generating Mhz > value from ratio for 'intel_gpu_freq_change' trace event. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92591 > Reported-by: Eero Tamminen <eero.t.tamminen@intel.com> > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index ebd6735..656c53a 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4330,7 +4330,7 @@ static void gen6_set_rps(struct drm_device *dev, u8 val) > POSTING_READ(GEN6_RPNSWREQ); > > dev_priv->rps.cur_freq = val; > - trace_intel_gpu_freq_change(val * 50); > + trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); I was thinking maybe moving it to the caller to avoid having it in both the gen6 and vlv set_rps functions, but there are actually so many callers that we're better off leaving it here. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > } > > static void valleyview_set_rps(struct drm_device *dev, u8 val) > -- > 2.5.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Tue, 17 Nov 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > On Tue, Nov 17, 2015 at 06:14:26PM +0200, Mika Kuoppala wrote: >> With gen < 9 we have had always 50Mhz units as our hw >> ratio. With gen >= 9 the hw ratio changed to 16.667Mhz (50/3). >> The result was that our gpu frequency tracing started to output >> values 3 times larger than expected due to hardcoded scaling >> value. Fix this by using Use intel_gpu_freq() when generating Mhz >> value from ratio for 'intel_gpu_freq_change' trace event. >> >> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92591 >> Reported-by: Eero Tamminen <eero.t.tamminen@intel.com> >> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> >> --- >> drivers/gpu/drm/i915/intel_pm.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c >> index ebd6735..656c53a 100644 >> --- a/drivers/gpu/drm/i915/intel_pm.c >> +++ b/drivers/gpu/drm/i915/intel_pm.c >> @@ -4330,7 +4330,7 @@ static void gen6_set_rps(struct drm_device *dev, u8 val) >> POSTING_READ(GEN6_RPNSWREQ); >> >> dev_priv->rps.cur_freq = val; >> - trace_intel_gpu_freq_change(val * 50); >> + trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); > > I was thinking maybe moving it to the caller to avoid having it in both > the gen6 and vlv set_rps functions, but there are actually so many callers > that we're better off leaving it here. > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Pushed to drm-intel-fixes with cc: stable for v4.3+, thanks for the patch and review. BR, Jani. > >> } >> >> static void valleyview_set_rps(struct drm_device *dev, u8 val) >> -- >> 2.5.0 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ebd6735..656c53a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4330,7 +4330,7 @@ static void gen6_set_rps(struct drm_device *dev, u8 val) POSTING_READ(GEN6_RPNSWREQ); dev_priv->rps.cur_freq = val; - trace_intel_gpu_freq_change(val * 50); + trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); } static void valleyview_set_rps(struct drm_device *dev, u8 val)
With gen < 9 we have had always 50Mhz units as our hw ratio. With gen >= 9 the hw ratio changed to 16.667Mhz (50/3). The result was that our gpu frequency tracing started to output values 3 times larger than expected due to hardcoded scaling value. Fix this by using Use intel_gpu_freq() when generating Mhz value from ratio for 'intel_gpu_freq_change' trace event. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92591 Reported-by: Eero Tamminen <eero.t.tamminen@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)