From patchwork Wed Nov 18 10:24:43 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tim.gore@intel.com X-Patchwork-Id: 7647911 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D99869F392 for ; Wed, 18 Nov 2015 10:24:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F16F0205EE for ; Wed, 18 Nov 2015 10:24:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id EAFD920434 for ; Wed, 18 Nov 2015 10:24:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 50A7672136; Wed, 18 Nov 2015 02:24:47 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 63A8672136 for ; Wed, 18 Nov 2015 02:24:46 -0800 (PST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP; 18 Nov 2015 02:24:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,312,1444719600"; d="scan'208";a="688352129" Received: from tgore-linux2.isw.intel.com ([10.102.226.103]) by orsmga003.jf.intel.com with ESMTP; 18 Nov 2015 02:24:44 -0800 From: tim.gore@intel.com To: intel-gfx@lists.freedesktop.org Date: Wed, 18 Nov 2015 10:24:43 +0000 Message-Id: <1447842283-4226-1-git-send-email-tim.gore@intel.com> X-Mailer: git-send-email 1.9.1 Cc: mika.kuoppala@linux.com, thomas.wood@intel.com Subject: [Intel-gfx] [PATCH i-g-t] tests/gem_reset_stats.c: prepare for per engine resets X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Tim Gore when checking to make sure that the driver has performed the expected number of resets, this test looks at the reset_count, which is incremented each time the GPU is reset. Upcoming changes in the way GPU hangs are handled mean that in most cases (and in all the cases in this test) only a single GPU engine is reset which does not cause the reset_count to be incremented. This is already causing this test to fail on Android. In this case we can instead look at the batch_active count which is also returned from the i915_get_reset_stats_ioctl and is incremented by both a single engine reset and a full gpu reset. There are differences between the reset_count and the batch_active count, but for establishing that the correct number of resets have occured either can be used. This change enables this test to run successfully on Android and will mean that the test does not break when the TDR patches get merged into the uptream driver. Signed-off-by: Tim Gore --- tests/gem_reset_stats.c | 41 ++++++++++++++++++++++++++--------------- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/tests/gem_reset_stats.c b/tests/gem_reset_stats.c index 4cbbb4e..5ec026f 100644 --- a/tests/gem_reset_stats.c +++ b/tests/gem_reset_stats.c @@ -104,9 +104,9 @@ static int gem_reset_stats(int fd, int ctx_id, rs->ctx_id = ctx_id; rs->flags = 0; - rs->reset_count = rand(); - rs->batch_active = rand(); - rs->batch_pending = rand(); + rs->reset_count = UINT32_MAX; + rs->batch_active = UINT32_MAX; + rs->batch_pending = UINT32_MAX; rs->pad = 0; do { @@ -690,6 +690,18 @@ static int get_reset_count(int fd, int ctx) return rs.reset_count; } +static int get_active_count(int fd, int ctx) +{ + int ret; + struct local_drm_i915_reset_stats rs; + + ret = gem_reset_stats(fd, ctx, &rs); + if (ret) + return ret; + + return rs.batch_active; +} + static void test_close_pending_ctx(void) { int fd, h; @@ -837,17 +849,16 @@ static void test_reset_count(const bool create_ctx) assert_reset_status(fd, ctx, RS_NO_ERROR); - c1 = get_reset_count(fd, ctx); - igt_assert(c1 >= 0); + c1 = get_active_count(fd, ctx); + igt_assert(c1 == 0); h = inject_hang(fd, ctx); igt_assert_lte(0, h); gem_sync(fd, h); assert_reset_status(fd, ctx, RS_BATCH_ACTIVE); - c2 = get_reset_count(fd, ctx); - igt_assert(c2 >= 0); - igt_assert(c2 == (c1 + 1)); + c2 = get_active_count(fd, ctx); + igt_assert(c2 == 1); igt_fork(child, 1) { igt_drop_root(); @@ -877,9 +888,9 @@ static int _test_params(int fd, int ctx, uint32_t flags, uint32_t pad) rs.ctx_id = ctx; rs.flags = flags; - rs.reset_count = rand(); - rs.batch_active = rand(); - rs.batch_pending = rand(); + rs.reset_count = UINT32_MAX; + rs.batch_active = UINT32_MAX; + rs.batch_pending = UINT32_MAX; rs.pad = pad; do { @@ -976,14 +987,14 @@ static void defer_hangcheck(int ring_num) igt_skip_on(next_ring == current_ring); - count_start = get_reset_count(fd, 0); - igt_assert_lte(0, count_start); + count_start = get_active_count(fd, 0); + igt_assert(count_start == 0); igt_assert(inject_hang_ring(fd, 0, current_ring->exec, true)); while (--seconds) { igt_assert(exec_valid_ring(fd, 0, next_ring->exec)); - count_end = get_reset_count(fd, 0); + count_end = get_active_count(fd, 0); igt_assert_lte(0, count_end); if (count_end > count_start) @@ -992,7 +1003,7 @@ static void defer_hangcheck(int ring_num) sleep(1); } - igt_assert_lt(count_start, count_end); + igt_assert(count_end == 1); close(fd); }