From patchwork Fri Nov 27 18:08:33 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marius Vlad X-Patchwork-Id: 7714311 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 854D09F4F5 for ; Fri, 27 Nov 2015 18:09:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9B2AC206A5 for ; Fri, 27 Nov 2015 18:09:18 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id A7932204B0 for ; Fri, 27 Nov 2015 18:09:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 35E3C6EC00; Fri, 27 Nov 2015 10:09:17 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id CB82C6EC00 for ; Fri, 27 Nov 2015 10:09:15 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP; 27 Nov 2015 10:09:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,352,1444719600"; d="scan'208";a="848500863" Received: from mcvlad-wk.rb.intel.com (HELO mcvlad-wk) ([10.237.105.57]) by fmsmga001.fm.intel.com with ESMTP; 27 Nov 2015 10:09:06 -0800 Received: by mcvlad-wk (Postfix, from userid 1000) id 411CEC0067; Fri, 27 Nov 2015 20:09:26 +0200 (EET) From: Marius Vlad To: intel-gfx@lists.freedesktop.org Date: Fri, 27 Nov 2015 20:08:33 +0200 Message-Id: <1448647713-7127-2-git-send-email-marius.c.vlad@intel.com> X-Mailer: git-send-email 2.6.2 In-Reply-To: <1448647713-7127-1-git-send-email-marius.c.vlad@intel.com> References: <1448386923-18141-1-git-send-email-marius.c.vlad@intel.com> <1448647713-7127-1-git-send-email-marius.c.vlad@intel.com> Subject: [Intel-gfx] [PATCH i-g-t] tests/pm_rpm tests for set_caching and set_tiling ioctl(s) X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Marius Vlad --- tests/pm_rpm.c | 114 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/tests/pm_rpm.c b/tests/pm_rpm.c index c4fb19c..e9ba9ea 100644 --- a/tests/pm_rpm.c +++ b/tests/pm_rpm.c @@ -1729,6 +1729,114 @@ static void planes_subtest(bool universal, bool dpms) } } +static void pm_test_tiling(void) +{ + uint32_t *handles; + uint8_t **gem_bufs; + + int max_gem_objs = 0; + uint8_t off_bit = 14; + uint32_t gtt_obj_max_size = (256 * 1024); + + uint32_t i, j, k, tiling_modes[3] = { + I915_TILING_NONE, + I915_TILING_X, + I915_TILING_Y, + }; + uint32_t ti, sw; + + /* default stride value */ + uint32_t stride = 512; + + /* calculate how many objects we can map */ + for (i = 1 << off_bit; i <= gtt_obj_max_size; i <<= 1, max_gem_objs++) + ; + + gem_bufs = calloc(max_gem_objs, sizeof(*gem_bufs)); + handles = calloc(max_gem_objs, sizeof(*handles)); + + /* try to set different tiling for each handle */ + for (i = 0; i < ARRAY_SIZE(tiling_modes); i++) { + + for (j = 0, k = 1 << off_bit; + k <= gtt_obj_max_size; k <<= 1, j++) { + handles[j] = gem_create(drm_fd, k); + gem_bufs[j] = gem_mmap__gtt(drm_fd, handles[j], + k, PROT_WRITE); + memset(gem_bufs[j], 0x0, k); + } + + disable_all_screens_and_wait(&ms_data); + + for (j = 0; j < max_gem_objs; j++) { + gem_set_tiling(drm_fd, handles[j], + tiling_modes[i], stride); + gem_get_tiling(drm_fd, handles[j], &ti, &sw); + igt_assert(tiling_modes[i] == ti); + } + + enable_one_screen_and_wait(&ms_data); + + for (j = 0, k = 1 << off_bit; + k <= gtt_obj_max_size; k <<= 1, j++) { + igt_assert(munmap(gem_bufs[j], k) == 0); + gem_close(drm_fd, handles[j]); + } + } + + free(gem_bufs); + free(handles); +} + +static void pm_test_caching(void) +{ + uint32_t handle; + uint8_t *gem_buf; + + uint32_t i, got_caching; + uint32_t gtt_obj_max_size = (16 * 1024); + uint32_t cache_levels[3] = { + I915_CACHING_NONE, + I915_CACHING_CACHED, /* LLC caching */ + I915_CACHING_DISPLAY, /* eDRAM caching */ + }; + + + handle = gem_create(drm_fd, gtt_obj_max_size); + gem_buf = gem_mmap__gtt(drm_fd, handle, gtt_obj_max_size, PROT_WRITE); + + for (i = 0; i < ARRAY_SIZE(cache_levels); i++) { + memset(gem_buf, 16 << i, gtt_obj_max_size); + + disable_all_screens_and_wait(&ms_data); + + igt_debug("Setting cache level %u\n", cache_levels[i]); + + gem_set_caching(drm_fd, handle, cache_levels[i]); + + got_caching = gem_get_caching(drm_fd, handle); + + igt_debug("Got back %u\n", got_caching); + + /* + * Allow fall-back to CACHING_NONE in case the platform does + * not support it. + */ + if (cache_levels[i] == I915_CACHING_DISPLAY) + igt_assert(got_caching == I915_CACHING_NONE || + got_caching == I915_CACHING_DISPLAY); + else + igt_assert(got_caching == cache_levels[i]); + + enable_one_screen_and_wait(&ms_data); + } + + igt_assert(munmap(gem_buf, gtt_obj_max_size) == 0); + gem_close(drm_fd, handle); +} + + + static void fences_subtest(bool dpms) { int i; @@ -1927,6 +2035,12 @@ int main(int argc, char *argv[]) igt_subtest("gem-execbuf-stress-extra-wait") gem_execbuf_stress_subtest(rounds, WAIT_STATUS | WAIT_EXTRA); + /* power-wake reference tests */ + igt_subtest("pm-tiling") + pm_test_tiling(); + igt_subtest("pm-caching") + pm_test_caching(); + igt_fixture teardown_environment();