| Message ID | 1448893432-6978-6-git-send-email-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, 30 Nov 2015, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Currently we round the AUX clock divider down on g4x, to closest > on HSW/BDW port A, and up everywhere else. We are supposed to get > as close to 2MHz as we can, so round to closest seems like the > best option. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Makes sense. Reviewed-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 77ae5821e9c0..f335c92b4fa7 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -681,7 +681,7 @@ static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) > * The clock divider is based off the hrawclk, and would like to run at > * 2MHz. So, take the hrawclk value and divide by 2 and use that > */ > - return index ? 0 : intel_hrawclk(dev) / 2; > + return index ? 0 : DIV_ROUND_CLOSEST(intel_hrawclk(dev), 2); > } > > static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) > @@ -694,10 +694,10 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) > return 0; > > if (intel_dig_port->port == PORT_A) { > - return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000); > + return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); > > } else { > - return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); > + return DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2); > } > } > > @@ -719,7 +719,7 @@ static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) > default: return 0; > } > } else { > - return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); > + return index ? 0 : DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2); > } > }
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 77ae5821e9c0..f335c92b4fa7 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -681,7 +681,7 @@ static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) * The clock divider is based off the hrawclk, and would like to run at * 2MHz. So, take the hrawclk value and divide by 2 and use that */ - return index ? 0 : intel_hrawclk(dev) / 2; + return index ? 0 : DIV_ROUND_CLOSEST(intel_hrawclk(dev), 2); } static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) @@ -694,10 +694,10 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) return 0; if (intel_dig_port->port == PORT_A) { - return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000); + return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); } else { - return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); + return DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2); } } @@ -719,7 +719,7 @@ static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) default: return 0; } } else { - return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); + return index ? 0 : DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2); } }