| Message ID | 1448967935-21760-1-git-send-email-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Dec 01, 2015 at 11:05:33AM +0000, Chris Wilson wrote: > This is just a little bit of syntatic sugar to hide the atomic_reads() > throughout the code to retrieve the current reset_counter. It also > provides the other utility functions to check the reset state on the > already read reset_counter, so that we can read it once and do multiple > tests rather than risk the value changing between tests. This patch also changes the meaning of reset_in_progress to not include WEDGED afaict. I agree with that change, but it needs to be mentioned in the commit message. Also with that change there's some cleanup potential since a bunch of callers that explicitly checked for reset_in_progress && !terminally_wedged now can drop the 2nd part of the condition. That simplification is why I've done this change in my patch. -Daniel > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 2 +- > drivers/gpu/drm/i915/i915_drv.h | 32 ++++++++++++++++++++++++++++---- > drivers/gpu/drm/i915/i915_gem.c | 12 ++++++------ > drivers/gpu/drm/i915/intel_display.c | 16 ++++++++++------ > drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- > 5 files changed, 46 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index bfd57fb597dc..864b3ae9419c 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -4656,7 +4656,7 @@ i915_wedged_get(void *data, u64 *val) > struct drm_device *dev = data; > struct drm_i915_private *dev_priv = dev->dev_private; > > - *val = atomic_read(&dev_priv->gpu_error.reset_counter); > + *val = i915_reset_counter(&dev_priv->gpu_error); > > return 0; > } > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index d07041c1729d..2a4cfa06c28d 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2979,20 +2979,44 @@ void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); > int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, > bool interruptible); > > +static inline u32 i915_reset_counter(struct i915_gpu_error *error) > +{ > + return atomic_read(&error->reset_counter); > +} > + > +static inline bool __i915_reset_in_progress(u32 reset) > +{ > + return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG); > +} > + > +static inline bool __i915_reset_in_progress_or_wedged(u32 reset) > +{ > + return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); > +} > + > +static inline bool __i915_terminally_wedged(u32 reset) > +{ > + return unlikely(reset & I915_WEDGED); > +} > + > static inline bool i915_reset_in_progress(struct i915_gpu_error *error) > { > - return unlikely(atomic_read(&error->reset_counter) > - & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); > + return __i915_reset_in_progress(i915_reset_counter(error)); > +} > + > +static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error) > +{ > + return __i915_reset_in_progress_or_wedged(i915_reset_counter(error)); > } > > static inline bool i915_terminally_wedged(struct i915_gpu_error *error) > { > - return atomic_read(&error->reset_counter) & I915_WEDGED; > + return __i915_terminally_wedged(i915_reset_counter(error)); > } > > static inline u32 i915_reset_count(struct i915_gpu_error *error) > { > - return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; > + return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2; > } > > static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index cccfe5bfe5bf..bff245de8ade 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -1297,7 +1297,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req, > > /* We need to check whether any gpu reset happened in between > * the caller grabbing the seqno and now ... */ > - if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { > + if (reset_counter != i915_reset_counter(&dev_priv->gpu_error)) { > /* ... but upgrade the -EAGAIN to an -EIO if the gpu > * is truely gone. */ > ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); > @@ -1475,7 +1475,7 @@ i915_wait_request(struct drm_i915_gem_request *req) > return ret; > > ret = __i915_wait_request(req, > - atomic_read(&dev_priv->gpu_error.reset_counter), > + i915_reset_counter(&dev_priv->gpu_error), > interruptible, NULL, NULL); > if (ret) > return ret; > @@ -1564,7 +1564,7 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, > if (ret) > return ret; > > - reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); > + reset_counter = i915_reset_counter(&dev_priv->gpu_error); > > if (readonly) { > struct drm_i915_gem_request *req; > @@ -3110,7 +3110,7 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > } > > drm_gem_object_unreference(&obj->base); > - reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); > + reset_counter = i915_reset_counter(&dev_priv->gpu_error); > > for (i = 0; i < I915_NUM_RINGS; i++) { > if (obj->last_read_req[i] == NULL) > @@ -3155,7 +3155,7 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj, > if (!i915_semaphore_is_enabled(obj->base.dev)) { > struct drm_i915_private *i915 = to_i915(obj->base.dev); > ret = __i915_wait_request(from_req, > - atomic_read(&i915->gpu_error.reset_counter), > + i915_reset_counter(&i915->gpu_error), > i915->mm.interruptible, > NULL, > &i915->rps.semaphores); > @@ -4109,7 +4109,7 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) > > target = request; > } > - reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); > + reset_counter = i915_reset_counter(&dev_priv->gpu_error); > if (target) > i915_gem_request_reference(target); > spin_unlock(&file_priv->mm.lock); > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 4ae490dfe2c4..511ead08ccd8 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -3287,10 +3287,12 @@ static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) > struct drm_device *dev = crtc->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > + unsigned reset_counter; > bool pending; > > - if (i915_reset_in_progress(&dev_priv->gpu_error) || > - intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) > + reset_counter = i915_reset_counter(&dev_priv->gpu_error); > + if (intel_crtc->reset_counter != reset_counter || > + __i915_reset_in_progress(reset_counter)) > return false; > > spin_lock_irq(&dev->event_lock); > @@ -10865,9 +10867,11 @@ static bool page_flip_finished(struct intel_crtc *crtc) > { > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > + unsigned reset_counter; > > - if (i915_reset_in_progress(&dev_priv->gpu_error) || > - crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) > + reset_counter = i915_reset_counter(&dev_priv->gpu_error); > + if (crtc->reset_counter != reset_counter || > + __i915_reset_in_progress(reset_counter)) > return true; > > /* > @@ -11511,7 +11515,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, > goto cleanup; > > atomic_inc(&intel_crtc->unpin_work_count); > - intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); > + intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error); > > if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) > work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; > @@ -13303,7 +13307,7 @@ static int intel_atomic_prepare_commit(struct drm_device *dev, > if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { > u32 reset_counter; > > - reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); > + reset_counter = i915_reset_counter(&dev_priv->gpu_error); > mutex_unlock(&dev->struct_mutex); > > for_each_plane_in_state(state, plane, plane_state, i) { > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 57d78f264b53..8970267d27bb 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -2286,7 +2286,7 @@ int intel_ring_idle(struct intel_engine_cs *ring) > > /* Make sure we do not trigger any retires */ > return __i915_wait_request(req, > - atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter), > + i915_reset_counter(&to_i915(ring->dev)->gpu_error), > to_i915(ring->dev)->mm.interruptible, > NULL, NULL); > } > -- > 2.6.2 >
On Thu, Dec 03, 2015 at 09:57:01AM +0100, Daniel Vetter wrote: > On Tue, Dec 01, 2015 at 11:05:33AM +0000, Chris Wilson wrote: > > This is just a little bit of syntatic sugar to hide the atomic_reads() > > throughout the code to retrieve the current reset_counter. It also > > provides the other utility functions to check the reset state on the > > already read reset_counter, so that we can read it once and do multiple > > tests rather than risk the value changing between tests. > > This patch also changes the meaning of reset_in_progress to not include > WEDGED afaict. I agree with that change, but it needs to be mentioned in > the commit message. > > Also with that change there's some cleanup potential since a bunch of > callers that explicitly checked for reset_in_progress && > !terminally_wedged now can drop the 2nd part of the condition. That > simplification is why I've done this change in my patch. I was just splitting out the header change and simplest of seds from the complete patch. Changing the reset/recovery interfaces I left till last. -Chris
On Thu, Dec 03, 2015 at 09:02:16AM +0000, Chris Wilson wrote: > On Thu, Dec 03, 2015 at 09:57:01AM +0100, Daniel Vetter wrote: > > On Tue, Dec 01, 2015 at 11:05:33AM +0000, Chris Wilson wrote: > > > This is just a little bit of syntatic sugar to hide the atomic_reads() > > > throughout the code to retrieve the current reset_counter. It also > > > provides the other utility functions to check the reset state on the > > > already read reset_counter, so that we can read it once and do multiple > > > tests rather than risk the value changing between tests. > > > > This patch also changes the meaning of reset_in_progress to not include > > WEDGED afaict. I agree with that change, but it needs to be mentioned in > > the commit message. > > > > Also with that change there's some cleanup potential since a bunch of > > callers that explicitly checked for reset_in_progress && > > !terminally_wedged now can drop the 2nd part of the condition. That > > simplification is why I've done this change in my patch. > > I was just splitting out the header change and simplest of seds from the > complete patch. Changing the reset/recovery interfaces I left till last. I've found at least 1 huk I was looking for in patch 3. The other is in reset_and_wakeup, and I think it's better to change the control flow there differently. See my "[PATCH] drm/i915: Fix up -EIO ABI per igt/gem_eio" for what I think should be changed around terminally_wedged() calls if you drop the terminal state from reset_in_progress(). -Daniel
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index bfd57fb597dc..864b3ae9419c 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4656,7 +4656,7 @@ i915_wedged_get(void *data, u64 *val) struct drm_device *dev = data; struct drm_i915_private *dev_priv = dev->dev_private; - *val = atomic_read(&dev_priv->gpu_error.reset_counter); + *val = i915_reset_counter(&dev_priv->gpu_error); return 0; } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d07041c1729d..2a4cfa06c28d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2979,20 +2979,44 @@ void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, bool interruptible); +static inline u32 i915_reset_counter(struct i915_gpu_error *error) +{ + return atomic_read(&error->reset_counter); +} + +static inline bool __i915_reset_in_progress(u32 reset) +{ + return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG); +} + +static inline bool __i915_reset_in_progress_or_wedged(u32 reset) +{ + return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); +} + +static inline bool __i915_terminally_wedged(u32 reset) +{ + return unlikely(reset & I915_WEDGED); +} + static inline bool i915_reset_in_progress(struct i915_gpu_error *error) { - return unlikely(atomic_read(&error->reset_counter) - & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); + return __i915_reset_in_progress(i915_reset_counter(error)); +} + +static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error) +{ + return __i915_reset_in_progress_or_wedged(i915_reset_counter(error)); } static inline bool i915_terminally_wedged(struct i915_gpu_error *error) { - return atomic_read(&error->reset_counter) & I915_WEDGED; + return __i915_terminally_wedged(i915_reset_counter(error)); } static inline u32 i915_reset_count(struct i915_gpu_error *error) { - return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; + return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2; } static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index cccfe5bfe5bf..bff245de8ade 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1297,7 +1297,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req, /* We need to check whether any gpu reset happened in between * the caller grabbing the seqno and now ... */ - if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { + if (reset_counter != i915_reset_counter(&dev_priv->gpu_error)) { /* ... but upgrade the -EAGAIN to an -EIO if the gpu * is truely gone. */ ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); @@ -1475,7 +1475,7 @@ i915_wait_request(struct drm_i915_gem_request *req) return ret; ret = __i915_wait_request(req, - atomic_read(&dev_priv->gpu_error.reset_counter), + i915_reset_counter(&dev_priv->gpu_error), interruptible, NULL, NULL); if (ret) return ret; @@ -1564,7 +1564,7 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, if (ret) return ret; - reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); + reset_counter = i915_reset_counter(&dev_priv->gpu_error); if (readonly) { struct drm_i915_gem_request *req; @@ -3110,7 +3110,7 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) } drm_gem_object_unreference(&obj->base); - reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); + reset_counter = i915_reset_counter(&dev_priv->gpu_error); for (i = 0; i < I915_NUM_RINGS; i++) { if (obj->last_read_req[i] == NULL) @@ -3155,7 +3155,7 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj, if (!i915_semaphore_is_enabled(obj->base.dev)) { struct drm_i915_private *i915 = to_i915(obj->base.dev); ret = __i915_wait_request(from_req, - atomic_read(&i915->gpu_error.reset_counter), + i915_reset_counter(&i915->gpu_error), i915->mm.interruptible, NULL, &i915->rps.semaphores); @@ -4109,7 +4109,7 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) target = request; } - reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); + reset_counter = i915_reset_counter(&dev_priv->gpu_error); if (target) i915_gem_request_reference(target); spin_unlock(&file_priv->mm.lock); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4ae490dfe2c4..511ead08ccd8 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3287,10 +3287,12 @@ static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + unsigned reset_counter; bool pending; - if (i915_reset_in_progress(&dev_priv->gpu_error) || - intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) + reset_counter = i915_reset_counter(&dev_priv->gpu_error); + if (intel_crtc->reset_counter != reset_counter || + __i915_reset_in_progress(reset_counter)) return false; spin_lock_irq(&dev->event_lock); @@ -10865,9 +10867,11 @@ static bool page_flip_finished(struct intel_crtc *crtc) { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; + unsigned reset_counter; - if (i915_reset_in_progress(&dev_priv->gpu_error) || - crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) + reset_counter = i915_reset_counter(&dev_priv->gpu_error); + if (crtc->reset_counter != reset_counter || + __i915_reset_in_progress(reset_counter)) return true; /* @@ -11511,7 +11515,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, goto cleanup; atomic_inc(&intel_crtc->unpin_work_count); - intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); + intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error); if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; @@ -13303,7 +13307,7 @@ static int intel_atomic_prepare_commit(struct drm_device *dev, if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { u32 reset_counter; - reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); + reset_counter = i915_reset_counter(&dev_priv->gpu_error); mutex_unlock(&dev->struct_mutex); for_each_plane_in_state(state, plane, plane_state, i) { diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 57d78f264b53..8970267d27bb 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -2286,7 +2286,7 @@ int intel_ring_idle(struct intel_engine_cs *ring) /* Make sure we do not trigger any retires */ return __i915_wait_request(req, - atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter), + i915_reset_counter(&to_i915(ring->dev)->gpu_error), to_i915(ring->dev)->mm.interruptible, NULL, NULL); }
This is just a little bit of syntatic sugar to hide the atomic_reads() throughout the code to retrieve the current reset_counter. It also provides the other utility functions to check the reset state on the already read reset_counter, so that we can read it once and do multiple tests rather than risk the value changing between tests. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 32 ++++++++++++++++++++++++++++---- drivers/gpu/drm/i915/i915_gem.c | 12 ++++++------ drivers/gpu/drm/i915/intel_display.c | 16 ++++++++++------ drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- 5 files changed, 46 insertions(+), 18 deletions(-)