| Message ID | 1449238659-12473-3-git-send-email-m.deepak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Dec 04, 2015 at 07:47:39PM +0530, Deepak M wrote: > Additional clock value divider should use the ceil > value of the calulation to get the correct divider value. > > Signed-off-by: Deepak M <m.deepak@intel.com> > --- > drivers/gpu/drm/i915/intel_dsi_pll.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c > index cb3cf39..1322a71 100644 > --- a/drivers/gpu/drm/i915/intel_dsi_pll.c > +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c > @@ -454,7 +454,7 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port) > dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; > > /* Max possible output of clock is 39.5 MHz, program value -1 */ > - divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1; > + divider = DIV_ROUND_UP(dsi_rate, BXT_MAX_VAR_OUTPUT_KHZ) - 1; I can't find anything to support the 39.5 MHz claim above. I do know the tx escape clock should be <=20Mhz, so with the /2 extra divider it seems we should aim for <=40Mhz here. So yes, round up does make sense, but it seems to me that BXT_MAX_VAR_OUTPUT_KHZ should be 40 MHz. > tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider); > > /* > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> -----Original Message----- > From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com] > Sent: Friday, December 4, 2015 5:22 PM > To: Deepak, M <m.deepak@intel.com> > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use the ceil value for the > additional clk divider > > On Fri, Dec 04, 2015 at 07:47:39PM +0530, Deepak M wrote: > > Additional clock value divider should use the ceil value of the > > calulation to get the correct divider value. > > > > Signed-off-by: Deepak M <m.deepak@intel.com> > > --- > > drivers/gpu/drm/i915/intel_dsi_pll.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c > > b/drivers/gpu/drm/i915/intel_dsi_pll.c > > index cb3cf39..1322a71 100644 > > --- a/drivers/gpu/drm/i915/intel_dsi_pll.c > > +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c > > @@ -454,7 +454,7 @@ static void bxt_dsi_program_clocks(struct > drm_device *dev, enum port port) > > dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; > > > > /* Max possible output of clock is 39.5 MHz, program value -1 */ > > - divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1; > > + divider = DIV_ROUND_UP(dsi_rate, BXT_MAX_VAR_OUTPUT_KHZ) - > 1; > > I can't find anything to support the 39.5 MHz claim above. I do know the tx > escape clock should be <=20Mhz, so with the /2 extra divider it seems we > should aim for <=40Mhz here. So yes, round up does make sense, but it > seems to me that BXT_MAX_VAR_OUTPUT_KHZ should be 40 MHz. > [Deepak, M] Yes, thought about it and me too feel that it should be 40 MHz. We locally have tried with 2 different MIPI panels with 39.5 Mhz and didn't see any issue. I will confirm with SV teams and will update the patch accordingly. Thanks for pointing it :) > > tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider); > > > > /* > > -- > > 1.9.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrjälä > Intel OTC
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c index cb3cf39..1322a71 100644 --- a/drivers/gpu/drm/i915/intel_dsi_pll.c +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c @@ -454,7 +454,7 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port) dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; /* Max possible output of clock is 39.5 MHz, program value -1 */ - divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1; + divider = DIV_ROUND_UP(dsi_rate, BXT_MAX_VAR_OUTPUT_KHZ) - 1; tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider); /*
Additional clock value divider should use the ceil value of the calulation to get the correct divider value. Signed-off-by: Deepak M <m.deepak@intel.com> --- drivers/gpu/drm/i915/intel_dsi_pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)