From patchwork Wed Dec 9 15:01:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 7809261 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B01F2BEEE1 for ; Wed, 9 Dec 2015 15:02:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B6226204AE for ; Wed, 9 Dec 2015 15:02:12 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id D0FF120460 for ; Wed, 9 Dec 2015 15:02:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 466586E1B4; Wed, 9 Dec 2015 07:02:11 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id E2F7C6E1B4 for ; Wed, 9 Dec 2015 07:02:09 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP; 09 Dec 2015 07:01:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,404,1444719600"; d="scan'208";a="857317185" Received: from rosetta.fi.intel.com (HELO rosetta) ([10.237.72.66]) by fmsmga001.fm.intel.com with ESMTP; 09 Dec 2015 07:01:42 -0800 Received: by rosetta (Postfix, from userid 1000) id AC74E81941; Wed, 9 Dec 2015 17:01:41 +0200 (EET) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Wed, 9 Dec 2015 17:01:38 +0200 Message-Id: <1449673301-6449-1-git-send-email-mika.kuoppala@intel.com> X-Mailer: git-send-email 2.5.0 Cc: miku@iki.fi Subject: [Intel-gfx] [PATCH 1/4] drm/i915: Consolidate unclaimed reg detection X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Access the unclaimed reg detection register through one helper which also does cleanup. Note that we now access the register only if the platform has the actual non claimed access bit. This prevents needlessly reading the register with older gens when debug_mmio > 0. Cc: Chris Wilson Cc: Paulo Zanoni Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_uncore.c | 34 ++++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index c2358ba..9d672f7 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -334,13 +334,30 @@ static void intel_uncore_ellc_detect(struct drm_device *dev) } } +static bool +unclaimed_reg_access(struct drm_i915_private *dev_priv) +{ + u32 dbg; + + if (!HAS_FPGA_DBG_UNCLAIMED(dev_priv)) + return false; + + dbg = __raw_i915_read32(dev_priv, FPGA_DBG); + if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM))) + return false; + + __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); + + return true; +} + static void __intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake) { struct drm_i915_private *dev_priv = dev->dev_private; - if (HAS_FPGA_DBG_UNCLAIMED(dev)) - __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); + /* clear out unclaimed reg detection bit */ + unclaimed_reg_access(dev_priv); /* clear out old GT FIFO errors */ if (IS_GEN6(dev) || IS_GEN7(dev)) @@ -601,10 +618,9 @@ hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, if (!i915.mmio_debug) return; - if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { + if (unclaimed_reg_access(dev_priv)) { WARN(1, "Unclaimed register detected %s %s register 0x%x\n", when, op, i915_mmio_reg_offset(reg)); - __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); i915.mmio_debug--; /* Only report the first N failures */ } } @@ -617,11 +633,10 @@ hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv) if (i915.mmio_debug || !mmio_debug_once) return; - if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { + if (unclaimed_reg_access(dev_priv)) { DRM_DEBUG("Unclaimed register detected, " "enabling oneshot unclaimed register reporting. " "Please use i915.mmio_debug=N for more information.\n"); - __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); i915.mmio_debug = mmio_debug_once--; } } @@ -1589,11 +1604,6 @@ bool intel_has_gpu_reset(struct drm_device *dev) void intel_uncore_check_errors(struct drm_device *dev) { - struct drm_i915_private *dev_priv = dev->dev_private; - - if (HAS_FPGA_DBG_UNCLAIMED(dev) && - (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { + if (unclaimed_reg_access(to_i915(dev))) DRM_ERROR("Unclaimed register before interrupt\n"); - __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); - } }