From patchwork Thu Dec 17 18:57:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lionel Landwerlin X-Patchwork-Id: 7876201 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id F0AB89F387 for ; Thu, 17 Dec 2015 18:58:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4292E203F7 for ; Thu, 17 Dec 2015 18:58:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 36CC220437 for ; Thu, 17 Dec 2015 18:58:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B927C6E2CD; Thu, 17 Dec 2015 10:58:11 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 6BD126E2DA for ; Thu, 17 Dec 2015 10:58:10 -0800 (PST) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP; 17 Dec 2015 10:58:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,442,1444719600"; d="scan'208";a="15070933" Received: from ddesurmo-mobl1.ger.corp.intel.com (HELO ivy.ger.corp.intel.com) ([10.252.43.166]) by fmsmga004.fm.intel.com with ESMTP; 17 Dec 2015 10:58:08 -0800 From: Lionel Landwerlin To: intel-gfx@lists.freedesktop.org Date: Thu, 17 Dec 2015 18:57:57 +0000 Message-Id: <1450378678-24296-6-git-send-email-lionel.g.landwerlin@intel.com> X-Mailer: git-send-email 2.6.3 In-Reply-To: <1450378678-24296-1-git-send-email-lionel.g.landwerlin@intel.com> References: <1450378678-24296-1-git-send-email-lionel.g.landwerlin@intel.com> Cc: Kausal Malladi Subject: [Intel-gfx] [PATCH 5/6] drm/i915/bdw+: Implement color management X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shashank Sharma Implement degamma, csc and gamma steps on BDW+. Signed-off-by: Shashank Sharma Signed-off-by: Kausal Malladi --- drivers/gpu/drm/i915/i915_drv.c | 14 + drivers/gpu/drm/i915/i915_reg.h | 43 ++- drivers/gpu/drm/i915/intel_color_manager.c | 451 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 20 ++ 4 files changed, 525 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 4396300..395e5ad 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -289,22 +289,30 @@ static const struct intel_device_info intel_haswell_m_info = { static const struct intel_device_info intel_broadwell_d_info = { HSW_FEATURES, .gen = 8, + .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, }; static const struct intel_device_info intel_broadwell_m_info = { HSW_FEATURES, .gen = 8, .is_mobile = 1, + .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, }; static const struct intel_device_info intel_broadwell_gt3d_info = { HSW_FEATURES, .gen = 8, + .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, }; static const struct intel_device_info intel_broadwell_gt3m_info = { HSW_FEATURES, .gen = 8, .is_mobile = 1, + .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, }; @@ -324,12 +332,16 @@ static const struct intel_device_info intel_skylake_info = { HSW_FEATURES, .is_skylake = 1, .gen = 9, + .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, }; static const struct intel_device_info intel_skylake_gt3_info = { HSW_FEATURES, .is_skylake = 1, .gen = 9, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, + .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, }; @@ -339,6 +351,8 @@ static const struct intel_device_info intel_broxton_info = { .gen = 9, .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, + .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .num_pipes = 3, .has_ddi = 1, .has_fpga_dbg = 1, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 36bb320..c4da842 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5748,11 +5748,19 @@ enum skl_disp_power_wells { /* legacy palette */ #define _LGC_PALETTE_A 0x4a000 #define _LGC_PALETTE_B 0x4a800 -#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) +#define _LGC_PALETTE_C 0x4b000 +#define LGC_PALETTE(pipe, i) _MMIO(_PIPE3(pipe, \ + _LGC_PALETTE_A, \ + _LGC_PALETTE_B, \ + _LGC_PALETTE_C) + (i) * 4) #define _GAMMA_MODE_A 0x4a480 #define _GAMMA_MODE_B 0x4ac80 -#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) +#define _GAMMA_MODE_C 0x4b480 +#define GAMMA_MODE(pipe) _MMIO(_PIPE3(pipe, \ + _GAMMA_MODE_A, \ + _GAMMA_MODE_B, \ + _GAMMA_MODE_C)) #define GAMMA_MODE_MODE_MASK (3 << 0) #define GAMMA_MODE_MODE_8BIT (0 << 0) #define GAMMA_MODE_MODE_10BIT (1 << 0) @@ -8178,6 +8186,35 @@ enum skl_disp_power_wells { #define _PIPE_CSC_BASE(pipe) \ (_PIPE3(pipe, PIPEA_CGM_CSC, PIPEB_CGM_CSC, PIPEC_CGM_CSC)) - +/* BDW gamma correction */ +#define PAL_PREC_INDEX_A 0x4A400 +#define PAL_PREC_INDEX_B 0x4AC00 +#define PAL_PREC_INDEX_C 0x4B400 +#define PAL_PREC_DATA_A 0x4A404 +#define PAL_PREC_DATA_B 0x4AC04 +#define PAL_PREC_DATA_C 0x4B404 +#define PAL_PREC_GC_MAX_A 0x4A410 +#define PAL_PREC_GC_MAX_B 0x4AC10 +#define PAL_PREC_GC_MAX_C 0x4B410 +#define PAL_PREC_EXT_GC_MAX_A 0x4A420 +#define PAL_PREC_EXT_GC_MAX_B 0x4AC20 +#define PAL_PREC_EXT_GC_MAX_C 0x4B420 + +#define _PREC_PAL_INDEX(pipe) \ + (_PIPE3(pipe, PAL_PREC_INDEX_A, PAL_PREC_INDEX_B, PAL_PREC_INDEX_C)) +#define _PREC_PAL_DATA(pipe) \ + (_PIPE3(pipe, PAL_PREC_DATA_A, PAL_PREC_DATA_B, PAL_PREC_DATA_C)) +#define _PREC_PAL_GC_MAX(pipe) \ + (_PIPE3(pipe, PAL_PREC_GC_MAX_A, PAL_PREC_GC_MAX_B, PAL_PREC_GC_MAX_C)) +#define _PREC_PAL_EXT_GC_MAX(pipe) \ + (_PIPE3(pipe, PAL_PREC_EXT_GC_MAX_A, PAL_PREC_EXT_GC_MAX_B, PAL_PREC_EXT_GC_MAX_C)) + + +/* BDW CSC correction */ +#define CSC_COEFF_A 0x49010 +#define CSC_COEFF_B 0x49110 +#define CSC_COEFF_C 0x49210 +#define _PIPE_CSC_COEFF(pipe) \ + (_PIPE3(pipe, CSC_COEFF_A, CSC_COEFF_B, CSC_COEFF_C)) #endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index 02eee98..bca07c1 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -27,6 +27,451 @@ #include "intel_color_manager.h" +static void bdw_write_8bit_gamma_legacy(struct drm_device *dev, + struct drm_r32g32b32 *correction_values, i915_reg_t palette) +{ + u16 blue_fract, green_fract, red_fract; + u32 blue, green, red; + u32 count = 0; + u32 word = 0; + struct drm_i915_private *dev_priv = dev->dev_private; + + while (count < BDW_8BIT_GAMMA_MAX_VALS) { + blue = correction_values[count].b32; + green = correction_values[count].g32; + red = correction_values[count].r32; + + /* + * Maximum possible gamma correction value supported + * for BDW is 0xFFFFFFFF, so clamp the values accordingly + */ + if (blue >= BDW_MAX_GAMMA) + blue = BDW_MAX_GAMMA; + if (green >= BDW_MAX_GAMMA) + green = BDW_MAX_GAMMA; + if (red >= BDW_MAX_GAMMA) + red = BDW_MAX_GAMMA; + + blue_fract = GET_BITS(blue, 16, 8); + green_fract = GET_BITS(green, 16, 8); + red_fract = GET_BITS(red, 16, 8); + + /* Blue (7:0) Green (15:8) and Red (23:16) */ + SET_BITS(word, blue_fract, 0, 8); + SET_BITS(word, green_fract, 8, 8); + SET_BITS(word, red_fract, 16, 8); + I915_WRITE(palette, word); + palette.reg += 4; + count++; + } +} + +static void bdw_write_10bit_gamma_precision(struct drm_device *dev, + struct drm_r32g32b32 *correction_values, i915_reg_t pal_prec_data, + u32 no_of_coeff) +{ + u16 blue_fract, green_fract, red_fract; + u32 word = 0; + u32 count = 0; + u32 blue, green, red; + struct drm_i915_private *dev_priv = dev->dev_private; + + while (count < no_of_coeff) { + + blue = correction_values[count].b32; + green = correction_values[count].g32; + red = correction_values[count].r32; + + /* + * Maximum possible gamma correction value supported + * for BDW is 0xFFFFFFFF, so clamp the values accordingly + */ + if (blue >= BDW_MAX_GAMMA) + blue = BDW_MAX_GAMMA; + if (green >= BDW_MAX_GAMMA) + green = BDW_MAX_GAMMA; + if (red >= BDW_MAX_GAMMA) + red = BDW_MAX_GAMMA; + + /* + * Gamma correction values are sent in 8.24 format + * with 8 int and 24 fraction bits. BDW 10 bit gamma + * unit expects correction registers to be programmed in + * 0.10 format, with 0 int and 16 fraction bits. So take + * MSB 10 bit values(bits 23-14) from the fraction part and + * prepare the correction registers. + */ + blue_fract = GET_BITS(blue, 14, 10); + green_fract = GET_BITS(green, 14, 10); + red_fract = GET_BITS(red, 14, 10); + + /* Arrange: Red (29:20) Green (19:10) and Blue (9:0) */ + SET_BITS(word, red_fract, 20, 10); + SET_BITS(word, green_fract, 10, 10); + SET_BITS(word, blue_fract, 0, 10); + I915_WRITE(pal_prec_data, word); + count++; + } + DRM_DEBUG_DRIVER("Gamma correction programmed\n"); +} + +static void bdw_write_12bit_gamma_precision(struct drm_device *dev, + struct drm_r32g32b32 *correction_values, i915_reg_t pal_prec_data, + enum pipe pipe) +{ + uint16_t blue_fract, green_fract, red_fract; + uint32_t gcmax; + uint32_t word = 0; + uint32_t count = 0; + i915_reg_t gcmax_reg; + u32 blue, green, red; + struct drm_i915_private *dev_priv = dev->dev_private; + + /* Program first 512 values in precision palette */ + while (count < BDW_12BIT_GAMMA_MAX_VALS - 1) { + + blue = correction_values[count].b32; + green = correction_values[count].g32; + red = correction_values[count].r32; + + /* + * Maximum possible gamma correction value supported + * for BDW is 0xFFFFFFFF, so clamp the values accordingly + */ + if (blue >= BDW_MAX_GAMMA) + blue = BDW_MAX_GAMMA; + if (green >= BDW_MAX_GAMMA) + green = BDW_MAX_GAMMA; + if (red >= BDW_MAX_GAMMA) + red = BDW_MAX_GAMMA; + + /* + * Framework's general gamma format is 8.24 (8 int 16 fraction) + * BDW Platform's supported gamma format is 16 bit correction + * values in 0.16 format. So extract higher 16 fraction bits + * from 8.24 gamma correction values. + */ + red_fract = GET_BITS(red, 8, 16); + green_fract = GET_BITS(green, 8, 16); + blue_fract = GET_BITS(blue, 8, 16); + + /* + * From the bspec: + * For 12 bit gamma correction, program precision palette + * with 16 bits per color in a 0.16 format with 0 integer and + * 16 fractional bits (upper 10 bits in odd indexes, lower 6 + * bits in even indexes) + */ + + /* Even index: Lower 6 bits from correction should go as MSB */ + SET_BITS(word, GET_BITS(red_fract, 0, 6), 24, 6); + SET_BITS(word, GET_BITS(green_fract, 0, 6), 14, 6); + SET_BITS(word, GET_BITS(blue_fract, 0, 6), 4, 6); + I915_WRITE(pal_prec_data, word); + + word = 0x0; + /* Odd index: Upper 10 bits of correction should go as MSB */ + SET_BITS(word, GET_BITS(red_fract, 6, 10), 20, 10); + SET_BITS(word, GET_BITS(green_fract, 6, 10), 10, 10); + SET_BITS(word, GET_BITS(blue_fract, 6, 10), 0, 10); + + I915_WRITE(pal_prec_data, word); + count++; + } + + /* Now program the 513th value in GCMAX regs */ + word = 0; + gcmax_reg = _MMIO(_PREC_PAL_GC_MAX(pipe)); + gcmax = min_t(u32, GET_BITS(correction_values[count].r32, 8, 17), + BDW_MAX_GAMMA); + SET_BITS(word, gcmax, 0, 17); + I915_WRITE(gcmax_reg, word); + gcmax_reg.reg += 4; + + word = 0; + gcmax = min_t(u32, GET_BITS(correction_values[count].g32, 8, 17), + BDW_MAX_GAMMA); + SET_BITS(word, gcmax, 0, 17); + I915_WRITE(gcmax_reg, word); + gcmax_reg.reg += 4; + + word = 0; + gcmax = min_t(u32, GET_BITS(correction_values[count].b32, 8, 17), + BDW_MAX_GAMMA); + SET_BITS(word, gcmax, 0, 17); + I915_WRITE(gcmax_reg, word); +} + +/* Apply unity gamma for gamma reset */ +static void bdw_reset_gamma(struct drm_i915_private *dev_priv, + enum pipe pipe) +{ + u16 count = 0; + u32 val; + i915_reg_t pal_prec_data = LGC_PALETTE(pipe, 0); + + DRM_DEBUG_DRIVER("\n"); + + /* Reset the palette for unit gamma */ + while (count < BDW_8BIT_GAMMA_MAX_VALS) { + /* Red (23:16) Green (15:8) and Blue (7:0) */ + val = (count << 16) | (count << 8) | count; + I915_WRITE(pal_prec_data, val); + pal_prec_data.reg += 4; + count++; + } +} + +static int bdw_set_gamma(struct drm_device *dev, struct drm_property_blob *blob, + struct drm_crtc *crtc) +{ + enum pipe pipe; + int num_samples; + i915_reg_t pal_prec_index, pal_prec_data; + u32 mode, index, word = 0; + struct drm_palette *gamma_data; + struct drm_crtc_state *state = crtc->state; + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_r32g32b32 *correction_values = NULL; + + if (WARN_ON(!blob)) + return -EINVAL; + + gamma_data = (struct drm_palette *)blob->data; + pipe = to_intel_crtc(crtc)->pipe; + num_samples = blob->length / sizeof(struct drm_r32g32b32); + + pal_prec_index = _MMIO(_PREC_PAL_INDEX(pipe)); + pal_prec_data = _MMIO(_PREC_PAL_DATA(pipe)); + correction_values = (struct drm_r32g32b32 *)&gamma_data->lut; + + switch (num_samples) { + case GAMMA_DISABLE_VALS: + /* Disable Gamma functionality on Pipe */ + DRM_DEBUG_DRIVER("Disabling gamma on Pipe %c\n", + pipe_name(pipe)); + if ((mode & GAMMA_MODE_MODE_MASK) == GAMMA_MODE_MODE_12BIT) + bdw_reset_gamma(dev_priv, pipe); + state->palette_after_ctm_blob = NULL; + word = GAMMA_MODE_MODE_8BIT; + break; + + case BDW_8BIT_GAMMA_MAX_VALS: + /* Legacy palette */ + bdw_write_8bit_gamma_legacy(dev, correction_values, + LGC_PALETTE(pipe, 0)); + word = GAMMA_MODE_MODE_8BIT; + break; + + case BDW_SPLITGAMMA_MAX_VALS: + index = num_samples; + index |= BDW_INDEX_AUTO_INCREMENT | BDW_INDEX_SPLIT_MODE; + I915_WRITE(pal_prec_index, index); + bdw_write_10bit_gamma_precision(dev, correction_values, + pal_prec_data, BDW_SPLITGAMMA_MAX_VALS); + word = GAMMA_MODE_MODE_SPLIT; + break; + + case BDW_12BIT_GAMMA_MAX_VALS: + index = BDW_INDEX_AUTO_INCREMENT; + I915_WRITE(pal_prec_index, index); + bdw_write_12bit_gamma_precision(dev, correction_values, + pal_prec_data, pipe); + word = GAMMA_MODE_MODE_12BIT; + break; + + case BDW_10BIT_GAMMA_MAX_VALS: + index = BDW_INDEX_AUTO_INCREMENT; + I915_WRITE(pal_prec_index, index); + bdw_write_10bit_gamma_precision(dev, correction_values, + pal_prec_data, BDW_10BIT_GAMMA_MAX_VALS); + word = GAMMA_MODE_MODE_10BIT; + break; + + default: + DRM_ERROR("Invalid number of samples\n"); + return -EINVAL; + } + + /* Set gamma mode on pipe control reg */ + mode = I915_READ(GAMMA_MODE(pipe)); + mode &= ~GAMMA_MODE_MODE_MASK; + I915_WRITE(GAMMA_MODE(pipe), mode | word); + DRM_DEBUG_DRIVER("Gamma applied on pipe %c\n", + pipe_name(pipe)); + return 0; +} + +static int bdw_set_degamma(struct drm_device *dev, + struct drm_property_blob *blob, struct drm_crtc *crtc) +{ + enum pipe pipe; + int num_samples; + u32 index, mode; + i915_reg_t pal_prec_index, pal_prec_data; + struct drm_palette *degamma_data; + struct drm_crtc_state *state = crtc->state; + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_r32g32b32 *correction_values = NULL; + + if (WARN_ON(!blob)) + return -EINVAL; + + degamma_data = (struct drm_palette *)blob->data; + pipe = to_intel_crtc(crtc)->pipe; + num_samples = blob->length / sizeof(struct drm_r32g32b32); + + switch (num_samples) { + case GAMMA_DISABLE_VALS: + /* Disable degamma on Pipe */ + mode = I915_READ(GAMMA_MODE(pipe)) & ~GAMMA_MODE_MODE_MASK; + I915_WRITE(GAMMA_MODE(pipe), mode | GAMMA_MODE_MODE_8BIT); + + state->palette_before_ctm_blob = NULL; + DRM_DEBUG_DRIVER("Disabling degamma on Pipe %c\n", + pipe_name(pipe)); + break; + + case BDW_SPLITGAMMA_MAX_VALS: + pal_prec_index = _MMIO(_PREC_PAL_INDEX(pipe)); + pal_prec_data = _MMIO(_PREC_PAL_DATA(pipe)); + correction_values = degamma_data->lut; + + index = BDW_INDEX_AUTO_INCREMENT | BDW_INDEX_SPLIT_MODE; + I915_WRITE(pal_prec_index, index); + + bdw_write_10bit_gamma_precision(dev, + correction_values, + pal_prec_data, + BDW_SPLITGAMMA_MAX_VALS); + + /* Enable degamma on Pipe */ + mode = I915_READ(GAMMA_MODE(pipe)); + mode &= ~GAMMA_MODE_MODE_MASK; + I915_WRITE(GAMMA_MODE(pipe), mode | GAMMA_MODE_MODE_SPLIT); + DRM_DEBUG_DRIVER("degamma correction enabled on Pipe %c\n", + pipe_name(pipe)); + break; + + default: + DRM_ERROR("Invalid number of samples\n"); + return -EINVAL; + } + return 0; +} + +static uint32_t bdw_prepare_csc_coeff(int64_t coeff) +{ + uint32_t reg_val, ls_bit_pos, exponent_bits, sign_bit = 0; + int32_t mantissa; + uint64_t abs_coeff; + + coeff = min_t(int64_t, coeff, BDW_CSC_COEFF_MAX_VAL); + coeff = max_t(int64_t, coeff, BDW_CSC_COEFF_MIN_VAL); + + abs_coeff = abs(coeff); + if (abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 3)) { + /* abs_coeff < 0.125 */ + exponent_bits = 3; + ls_bit_pos = 19; + } else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 3) && + abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 2)) { + /* abs_coeff >= 0.125 && val < 0.25 */ + exponent_bits = 2; + ls_bit_pos = 20; + } else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 2) + && abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 1)) { + /* abs_coeff >= 0.25 && val < 0.5 */ + exponent_bits = 1; + ls_bit_pos = 21; + } else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 1) + && abs_coeff < BDW_CSC_COEFF_UNITY_VAL) { + /* abs_coeff >= 0.5 && val < 1.0 */ + exponent_bits = 0; + ls_bit_pos = 22; + } else if (abs_coeff >= BDW_CSC_COEFF_UNITY_VAL && + abs_coeff < (BDW_CSC_COEFF_UNITY_VAL << 1)) { + /* abs_coeff >= 1.0 && val < 2.0 */ + exponent_bits = 7; + ls_bit_pos = 23; + } else { + /* abs_coeff >= 2.0 && val < 4.0 */ + exponent_bits = 6; + ls_bit_pos = 24; + } + + mantissa = GET_BITS_ROUNDOFF(abs_coeff, ls_bit_pos, CSC_MAX_VALS); + if (coeff < 0) + sign_bit = 1; + + reg_val = 0; + SET_BITS(reg_val, exponent_bits, 12, 3); + SET_BITS(reg_val, mantissa, 3, 9); + SET_BITS(reg_val, sign_bit, 15, 1); + return reg_val; +} + +static int bdw_set_csc(struct drm_device *dev, struct drm_property_blob *blob, + struct drm_crtc *crtc) +{ + enum pipe pipe; + enum plane plane; + int temp, word; + int count = 0; + u32 plane_ctl, mode; + i915_reg_t reg; + struct drm_ctm *csc_data; + struct drm_i915_private *dev_priv = dev->dev_private; + + if (WARN_ON(!blob)) + return -EINVAL; + + if (blob->length != sizeof(struct drm_ctm)) { + DRM_ERROR("Invalid length of data received\n"); + return -EINVAL; + } + + csc_data = (struct drm_ctm *)blob->data; + pipe = to_intel_crtc(crtc)->pipe; + plane = to_intel_crtc(crtc)->plane; + + plane_ctl = I915_READ(PLANE_CTL(pipe, plane)); + plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE; + I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); + reg = _MMIO(_PIPE_CSC_COEFF(pipe)); + + /* + * BDW CSC correction coefficients are written like this: + * first two values go in a pair, into first register(0:15 and 16:31) + * third one alone goes into second register (16:31). Same + * pattern repeats for 3 times = 3 * 3 = 9 values. + */ + while (count < CSC_MAX_VALS) { + word = 0; + temp = bdw_prepare_csc_coeff(csc_data->ctm_coeff[count++]); + SET_BITS(word, temp, 16, 16); + + temp = bdw_prepare_csc_coeff(csc_data->ctm_coeff[count++]); + SET_BITS(word, temp, 0, 16); + + I915_WRITE(reg, word); + reg.reg += 4; + + word = 0; + temp = bdw_prepare_csc_coeff(csc_data->ctm_coeff[count++]); + SET_BITS(word, temp, 16, 16); + I915_WRITE(reg, word); + reg.reg += 4; + } + + /* Enable CSC functionality */ + mode = I915_READ(PIPE_CSC_MODE(pipe)); + mode |= CSC_POSITION_BEFORE_GAMMA; + I915_WRITE(PIPE_CSC_MODE(pipe), mode); + DRM_DEBUG_DRIVER("CSC enabled on Pipe %c\n", pipe_name(pipe)); + return 0; +} + static u16 chv_prepare_csc_coeff(s64 csc_coeff) { u16 csc_s3_12_format = 0; @@ -314,6 +759,8 @@ void intel_color_manager_commit(struct drm_device *dev, /* Gamma correction is platform specific */ if (IS_CHERRYVIEW(dev)) ret = chv_set_gamma(dev, blob, crtc); + else if (IS_BROADWELL(dev) || IS_GEN9(dev)) + ret = bdw_set_gamma(dev, blob, crtc); if (ret) DRM_ERROR("set Gamma correction failed\n"); @@ -326,6 +773,8 @@ void intel_color_manager_commit(struct drm_device *dev, /* Degamma correction */ if (IS_CHERRYVIEW(dev)) ret = chv_set_degamma(dev, blob, crtc); + else if (IS_BROADWELL(dev) || IS_GEN9(dev)) + ret = bdw_set_degamma(dev, blob, crtc); if (ret) DRM_ERROR("set degamma correction failed\n"); @@ -338,6 +787,8 @@ void intel_color_manager_commit(struct drm_device *dev, /* CSC correction */ if (IS_CHERRYVIEW(dev)) ret = chv_set_csc(dev, blob, crtc); + else if (IS_BROADWELL(dev) || IS_GEN9(dev)) + ret = bdw_set_csc(dev, blob, crtc); if (ret) DRM_ERROR("set CSC correction failed\n"); diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index 04185ac..3ceec3d 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -89,3 +89,23 @@ #define CGM_GAMMA_EN (1 << 2) #define CGM_CSC_EN (1 << 1) #define CGM_DEGAMMA_EN (1 << 0) + +/* BDW CSC */ +/* 1.0000000 in S31.32 format */ +#define BDW_CSC_COEFF_UNITY_VAL 0x100000000 +/* 3.9921875 in S31.32 format */ +#define BDW_CSC_COEFF_MAX_VAL 0x3FE000000 +/*-4.000000 in S31.32 format */ +#define BDW_CSC_COEFF_MIN_VAL 0xFFFFFFFC00000000 + +/* Gamma on BDW */ +#define BDW_SPLITGAMMA_MAX_VALS 512 +#define BDW_8BIT_GAMMA_MAX_VALS 256 +#define BDW_10BIT_GAMMA_MAX_VALS 1024 +#define BDW_12BIT_GAMMA_MAX_VALS 513 +#define BDW_MAX_GAMMA ((1 << 24) - 1) +#define BDW_INDEX_AUTO_INCREMENT (1 << 15) +#define BDW_INDEX_SPLIT_MODE (1 << 31) + +/* Degamma on BDW */ +#define BDW_DEGAMMA_MAX_VALS 512