| Message ID | 1450401412-10538-1-git-send-email-benjamin.widawsky@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Ben Widawsky <benjamin.widawsky@intel.com> writes: > Compile tested only. > > Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> > --- > drivers/gpu/drm/i915/intel_lrc.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 42a7be1..a9bc207 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1466,7 +1466,8 @@ static int gen8_init_common_ring(struct intel_engine_cs *ring) > u8 next_context_status_buffer_hw; > > I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); > - I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); > + if (INTEL_INFO(ring->dev)->gen == 8) > + I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); > It seems that this has only been removed from render, other engines still has it on skl. -Mika > if (ring->status_page.obj) { > I915_WRITE(RING_HWS_PGA(ring->mmio_base), > -- > 2.6.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Fri, Dec 18, 2015 at 10:17:49AM +0200, Mika Kuoppala wrote: > Ben Widawsky <benjamin.widawsky@intel.com> writes: > > > Compile tested only. > > > > Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> > > --- > > drivers/gpu/drm/i915/intel_lrc.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > > index 42a7be1..a9bc207 100644 > > --- a/drivers/gpu/drm/i915/intel_lrc.c > > +++ b/drivers/gpu/drm/i915/intel_lrc.c > > @@ -1466,7 +1466,8 @@ static int gen8_init_common_ring(struct intel_engine_cs *ring) > > u8 next_context_status_buffer_hw; > > > > I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); > > - I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); > > + if (INTEL_INFO(ring->dev)->gen == 8) > > + I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); > > > > It seems that this has only been removed from render, > other engines still has it on skl. > > -Mika > Hmm. What I am looking at says EXCLUDE(SKL+) for BCS and VCS. Then for VECS it says HSW, BDW, CHV. So I guess we're not looking at the same thing :( > > if (ring->status_page.obj) { > > I915_WRITE(RING_HWS_PGA(ring->mmio_base), > > -- > > 2.6.4 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 42a7be1..a9bc207 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1466,7 +1466,8 @@ static int gen8_init_common_ring(struct intel_engine_cs *ring) u8 next_context_status_buffer_hw; I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); - I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); + if (INTEL_INFO(ring->dev)->gen == 8) + I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); if (ring->status_page.obj) { I915_WRITE(RING_HWS_PGA(ring->mmio_base),
Compile tested only. Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)