From patchwork Thu Dec 31 12:45:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Feceoru, Gabriel" X-Patchwork-Id: 7936251 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 87429BEEE5 for ; Thu, 31 Dec 2015 12:39:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 40D3620397 for ; Thu, 31 Dec 2015 12:39:26 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E5B5220121 for ; Thu, 31 Dec 2015 12:39:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 68A696E0AA; Thu, 31 Dec 2015 04:39:23 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 5EAAE6E0AA for ; Thu, 31 Dec 2015 04:39:22 -0800 (PST) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP; 31 Dec 2015 04:39:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,503,1444719600"; d="scan'208";a="21720013" Received: from gfeceoru-ms-7924.rb.intel.com ([10.237.105.33]) by fmsmga004.fm.intel.com with ESMTP; 31 Dec 2015 04:39:20 -0800 From: Gabriel Feceoru To: intel-gfx@lists.freedesktop.org Date: Thu, 31 Dec 2015 14:45:49 +0200 Message-Id: <1451565949-8523-1-git-send-email-gabriel.feceoru@intel.com> X-Mailer: git-send-email 1.9.1 Subject: [Intel-gfx] [PATCH] drm/i915: Add RPM references in the *_get_hw_state functions X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This gets rid of errors like: [ 906.286213] ------------[ cut here ]------------ [ 906.286233] WARNING: CPU: 0 PID: 12252 at drivers/gpu/drm/i915/intel_drv.h:1457 gen6_read32+0x1ca/0x1e0 [i915]() [ 906.286234] RPM wakelock ref not held during HW access [ 906.286235] Modules linked in: [ 906.286236] snd_hda_intel i915 drm_kms_helper drm msr snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic snd_hda_codec snd_hwdep x86_pkg_temp_thermal snd_hda_core i2c_algo_bit ehci_pci syscopyarea sysfillrect sysimgblt fb_sys_fops ehci_hcd r8169 xhci_pci mii xhci_hcd video [last unloaded: drm] [ 906.286246] CPU: 0 PID: 12252 Comm: kms_pipe_crc_ba Tainted: G U W 4.4.0-rc6+ #45 [ 906.286247] Hardware name: Dell Inc. Inspiron 3847/088DT1 , BIOS A06 01/15/2015 [ 906.286248] ffffffffc022c098 ffff880210dbbae0 ffffffff813e0e4f ffff880210dbbb28 [ 906.286250] ffff880210dbbb18 ffffffff8105f5f2 ffff8801fff40000 0000000000046040 [ 906.286251] ffff8801fff49170 ffff8801fff49170 ffff8801fff40000 ffff880210dbbb78 [ 906.286253] Call Trace: [ 906.286256] [] dump_stack+0x44/0x55 [ 906.286259] [] warn_slowpath_common+0x82/0xc0 [ 906.286261] [] warn_slowpath_fmt+0x4c/0x50 [ 906.286270] [] ? drm_property_free_blob+0x8c/0xb0 [drm] [ 906.286280] [] gen6_read32+0x1ca/0x1e0 [i915] [ 906.286283] [] ? mutex_lock+0x12/0x30 [ 906.286294] [] hsw_ddi_wrpll_get_hw_state+0x40/0x50 [i915] [ 906.286304] [] intel_atomic_commit+0xd41/0x1740 [i915] [ 906.286312] [] drm_atomic_commit+0x37/0x60 [drm] [ 906.286316] [] drm_atomic_helper_set_config+0x76/0xb0 [drm_kms_helper] [ 906.286323] [] ? drm_modeset_lock_all_ctx+0x9a/0xb0 [drm] [ 906.286329] [] drm_mode_set_config_internal+0x62/0x100 [drm] [ 906.286335] [] drm_mode_setcrtc+0x3cd/0x4e0 [drm] [ 906.286339] [] drm_ioctl+0x152/0x540 [drm] [ 906.286341] [] ? __wake_up+0x44/0x50 [ 906.286346] [] ? drm_mode_setplane+0x1b0/0x1b0 [drm] [ 906.286348] [] ? mntput+0x24/0x40 [ 906.286350] [] ? __fput+0x172/0x1e0 [ 906.286352] [] do_vfs_ioctl+0x288/0x460 [ 906.286353] [] ? ____fput+0xe/0x10 Signed-off-by: Gabriel Feceoru --- drivers/gpu/drm/i915/intel_ddi.c | 48 ++++++++++++++++++++++++++++++---------- 1 file changed, 36 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index e6408e5..4ba9f2c 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2014,15 +2014,18 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum intel_display_power_domain power_domain; u32 tmp; int i; + bool ret = false; power_domain = intel_display_port_power_domain(encoder); if (!intel_display_power_is_enabled(dev_priv, power_domain)) - return false; + return ret; + + intel_runtime_pm_get(dev_priv); tmp = I915_READ(DDI_BUF_CTL(port)); if (!(tmp & DDI_BUF_CTL_ENABLE)) - return false; + goto out; if (port == PORT_A) { tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); @@ -2040,7 +2043,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder, break; } - return true; + ret = true; + goto out; } else { for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); @@ -2048,17 +2052,19 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder, if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) { if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST) - return false; + goto out; *pipe = i; - return true; + ret = true; + goto out; } } } DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); - - return false; +out: + intel_runtime_pm_put(dev_priv); + return ret; } void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) @@ -2510,7 +2516,10 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) return false; + intel_runtime_pm_get(dev_priv); val = I915_READ(WRPLL_CTL(pll->id)); + intel_runtime_pm_put(dev_priv); + hw_state->wrpll = val; return val & WRPLL_PLL_ENABLE; @@ -2525,7 +2534,10 @@ static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv, if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) return false; + intel_runtime_pm_get(dev_priv); val = I915_READ(SPLL_CTL); + intel_runtime_pm_put(dev_priv); + hw_state->spll = val; return val & SPLL_PLL_ENABLE; @@ -2644,16 +2656,19 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, uint32_t val; unsigned int dpll; const struct skl_dpll_regs *regs = skl_dpll_regs; + bool ret = false; if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) - return false; + return ret; /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ dpll = pll->id + 1; + intel_runtime_pm_get(dev_priv); + val = I915_READ(regs[pll->id].ctl); if (!(val & LCPLL_PLL_ENABLE)) - return false; + goto out; val = I915_READ(DPLL_CTRL1); hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f; @@ -2664,6 +2679,9 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); } + ret = true; +out: + intel_runtime_pm_put(dev_priv); return true; } @@ -2931,13 +2949,16 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, { enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ uint32_t val; + bool ret = false; if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) - return false; + return ret; + + intel_runtime_pm_get(dev_priv); val = I915_READ(BXT_PORT_PLL_ENABLE(port)); if (!(val & PORT_PLL_ENABLE)) - return false; + goto out; hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port)); hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; @@ -2984,7 +3005,10 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, I915_READ(BXT_PORT_PCS_DW12_LN23(port))); hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; - return true; + ret = true; +out: + intel_runtime_pm_put(dev_priv); + return ret; } static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)