From patchwork Tue Jan 5 03:29:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masanari Iida X-Patchwork-Id: 7952551 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5FE849F3F6 for ; Tue, 5 Jan 2016 03:29:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7C3622034F for ; Tue, 5 Jan 2016 03:29:28 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id A347A2034E for ; Tue, 5 Jan 2016 03:29:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1223688E8E; Mon, 4 Jan 2016 19:29:27 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pf0-f179.google.com (mail-pf0-f179.google.com [209.85.192.179]) by gabe.freedesktop.org (Postfix) with ESMTPS id 03EE788E8E; Mon, 4 Jan 2016 19:29:26 -0800 (PST) Received: by mail-pf0-f179.google.com with SMTP id 78so214703580pfw.2; Mon, 04 Jan 2016 19:29:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=wdxMY25at1y7T5Hss77x1sRf13hFFUXWn8dbsTV+9hs=; b=b9owV+mI6+3xfoIAcGkJ0Bb4MgrGZoVd+2cO48q+8CTNPzzI7o6liFld64/bndkRcE ahmA6uCyokNxvQIBOHO7D9Ga2DjYyqJzqNzWU0ZN0Ohcyfy/r5Tf0QCkrEgQbnb/NekV uWiDo3liqh2ieElh3TG6GYgmAKYGuEOG+AH/cMonf2aJ2KlqXK9HLneVWx7fRt/CRzja +lowkFyz9Qoic/iEkuU5cxgOz9AvDvdnbWddnvTY6LpE88By9ki3/vv39GL2SC7wLI1u ZFcr8T8Kt4cAJeuIx6OUlCLcBCpta4YduTZ8fczCLb0KK4GSL80eMfVuLiTNbl+0liev 1lKg== X-Received: by 10.98.87.69 with SMTP id l66mr50893057pfb.85.1451964565708; Mon, 04 Jan 2016 19:29:25 -0800 (PST) Received: from masabert (p652164-omed01.tokyo.ocn.ne.jp. [153.154.203.164]) by smtp.gmail.com with ESMTPSA id h90sm88516127pfj.23.2016.01.04.19.29.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Jan 2016 19:29:25 -0800 (PST) Received: by masabert (Postfix, from userid 1000) id 63BACE208C; Tue, 5 Jan 2016 12:29:21 +0900 (JST) From: Masanari Iida To: linux-kernel@vger.kernel.org, daniel.vetter@intel.com, trivial@kernel.org, jani.nikula@linux.intel.com, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, rdunlap@infradead.org Date: Tue, 5 Jan 2016 12:29:17 +0900 Message-Id: <1451964557-1145-1-git-send-email-standby24x7@gmail.com> X-Mailer: git-send-email 2.7.0.rc3 Cc: Masanari Iida , corbet@lwn.net Subject: [Intel-gfx] [PATCH] [trivial] drm/i915 Fix typos in i915_gem_fence.c X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch fix some spelling typos found in Documentation/Docbook gpu/ch04s03.html. This file was generated from comments within source, so I have to fix typos in i915_gem_fence.c. Signed-off-by: Masanari Iida Acked-by: Randy Dunlap --- drivers/gpu/drm/i915/i915_gem_fence.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c index 5981985..a2b938e 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence.c +++ b/drivers/gpu/drm/i915/i915_gem_fence.c @@ -34,8 +34,8 @@ * set of these objects. * * Fences are used to detile GTT memory mappings. They're also connected to the - * hardware frontbuffer render tracking and hence interract with frontbuffer - * conmpression. Furthermore on older platforms fences are required for tiled + * hardware frontbuffer render tracking and hence interact with frontbuffer + * compression. Furthermore on older platforms fences are required for tiled * objects used by the display engine. They can also be used by the render * engine - they're required for blitter commands and are optional for render * commands. But on gen4+ both display (with the exception of fbc) and rendering @@ -46,8 +46,8 @@ * * Finally note that because fences are such a restricted resource they're * dynamically associated with objects. Furthermore fence state is committed to - * the hardware lazily to avoid unecessary stalls on gen2/3. Therefore code must - * explictly call i915_gem_object_get_fence() to synchronize fencing status + * the hardware lazily to avoid unnecessary stalls on gen2/3. Therefore code must + * explicitly call i915_gem_object_get_fence() to synchronize fencing status * for cpu access. Also note that some code wants an unfenced view, for those * cases the fence can be removed forcefully with i915_gem_object_put_fence(). * @@ -527,7 +527,7 @@ void i915_gem_restore_fences(struct drm_device *dev) * required. * * When bit 17 is XORed in, we simply refuse to tile at all. Bit - * 17 is not just a page offset, so as we page an objet out and back in, + * 17 is not just a page offset, so as we page an object out and back in, * individual pages in it will have different bit 17 addresses, resulting in * each 64 bytes being swapped with its neighbor! *