From patchwork Mon Jan 11 09:16:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 8000061 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 01414BEEE5 for ; Mon, 11 Jan 2016 09:20:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2312720251 for ; Mon, 11 Jan 2016 09:20:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 4EDAF201FE for ; Mon, 11 Jan 2016 09:20:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 837756E243; Mon, 11 Jan 2016 01:19:58 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-f65.google.com (mail-wm0-f65.google.com [74.125.82.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 65AA46E237 for ; Mon, 11 Jan 2016 01:19:54 -0800 (PST) Received: by mail-wm0-f65.google.com with SMTP id l65so25311271wmf.3 for ; Mon, 11 Jan 2016 01:19:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=XUc42psfcXEugl2X7wrp5dW4AGoe6LFCj3w3GZnuKv4=; b=i/FrBk2H0vMu8xEm+T8K3vKmRBGM/l18qBSkZCThZy5L9SMizL4dNRKmsJGWVRm0ks R4swVCaKmo+Olm89p9qeEgtFpJHHvj1IbEiLdSdOQiLJEWDL2i1p22vqRX2p9rEEW9dy tVzqD2B2WR4/dUgorQ1O83JFEHISgYVGJfJ0C9jrLG8ZR4ZwCM18W8haHAoPZV2ikw8I JYf+zCLjZq5djfV/gnwOVU+qTO2GJNEeFawLRcC1ZrCndIdRX0BV38N/bQV2G+hjlXYB q43VGiD/Rzu+h4fuKwNUCRrqoHREfrKhMxVrFr3Y31dud+GzV2eheOcVTCEGoNQQQk58 5v2w== X-Received: by 10.194.157.165 with SMTP id wn5mr116162462wjb.41.1452503993225; Mon, 11 Jan 2016 01:19:53 -0800 (PST) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id v2sm11834679wmv.12.2016.01.11.01.19.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 11 Jan 2016 01:19:52 -0800 (PST) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Mon, 11 Jan 2016 09:16:28 +0000 Message-Id: <1452503961-14837-17-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.7.0.rc3 In-Reply-To: <1452503961-14837-1-git-send-email-chris@chris-wilson.co.uk> References: <1452503961-14837-1-git-send-email-chris@chris-wilson.co.uk> Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 017/190] drm/i915: Remove forcewake dance from seqno/irq barrier on legacy gen6+ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In order to ensure seqno/irq coherency, we current read a ring register. We are not sure quite how it works, only that is does. Experiments show that e.g. doing a clflush(seqno) instead is not sufficient, but we can remove the forcewake dance from the mmio access. v2: Baytrail wants a clflush too. Signed-off-by: Chris Wilson Cc: Daniel Vetter --- drivers/gpu/drm/i915/intel_ringbuffer.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 99780b674311..a1d43b2c7077 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1490,10 +1490,21 @@ gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) { /* Workaround to force correct ordering between irq and seqno writes on * ivb (and maybe also on snb) by reading from a CS register (like - * ACTHD) before reading the status page. */ + * ACTHD) before reading the status page. + * + * Note that this effectively effectively stalls the read by the time + * it takes to do a memory transaction, which more or less ensures + * that the write from the GPU has sufficient time to invalidate + * the CPU cacheline. Alternatively we could delay the interrupt from + * the CS ring to give the write time to land, but that would incur + * a delay after every batch i.e. much more frequent than a delay + * when waiting for the interrupt (with the same net latency). + */ if (!lazy_coherency) { struct drm_i915_private *dev_priv = ring->dev->dev_private; - POSTING_READ(RING_ACTHD(ring->mmio_base)); + POSTING_READ_FW(RING_ACTHD(ring->mmio_base)); + + intel_flush_status_page(ring, I915_GEM_HWS_INDEX); } return intel_read_status_page(ring, I915_GEM_HWS_INDEX);