From patchwork Mon Jan 11 09:17:04 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 8000661 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6F895BEEED for ; Mon, 11 Jan 2016 09:23:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3779F20251 for ; Mon, 11 Jan 2016 09:23:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 95F9620256 for ; Mon, 11 Jan 2016 09:23:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 387226E27B; Mon, 11 Jan 2016 01:23:02 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-f65.google.com (mail-wm0-f65.google.com [74.125.82.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9183D6E24F for ; Mon, 11 Jan 2016 01:20:37 -0800 (PST) Received: by mail-wm0-f65.google.com with SMTP id b14so25374776wmb.1 for ; Mon, 11 Jan 2016 01:20:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=SXVircfnr5eUR28bjc1LzjNHPKzon7kYgLZVT2Pd7VM=; b=AOPsA1BJR4kRaBSBcBCOMyjiWss5Co3crHHoYw4xQX13fi1OskgfGP6B7TTFjNvcNQ 41sM5smnmOwnEiKYRs4ry666Y8w+dgM+qLiIZXfn3zEmUGQBXZyjTskPl6H5GqhyX5DS mKTWt1zrA8dHKOZafXXgt8eOEDIo5aJAdNBNLtzHoMRpKeo1SzcLyXDqRLyY71ztrXlo t0XN70mfFo9wVn8O3sXGDxtYbKG22vSRXPGhF9D5gf+kkq3o+VaGCMzcS1WceRnZJXkK kYLQGSf8ObJCTLTxpHs5xFZ1OnVc9Mu4j3zleM5QJykooP+IAMKqEbsCeEvOSNvzlURh 1FWQ== X-Received: by 10.194.11.66 with SMTP id o2mr150561124wjb.103.1452504036337; Mon, 11 Jan 2016 01:20:36 -0800 (PST) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id v2sm11834679wmv.12.2016.01.11.01.20.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 11 Jan 2016 01:20:35 -0800 (PST) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Mon, 11 Jan 2016 09:17:04 +0000 Message-Id: <1452503961-14837-53-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.7.0.rc3 In-Reply-To: <1452503961-14837-1-git-send-email-chris@chris-wilson.co.uk> References: <1452503961-14837-1-git-send-email-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 053/190] drm/i915: Convert i915_semaphores_is_enabled over to early sanitize X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Rather than recomputing whether semaphores are enabled, we can do that computation once during early initialisation as the i915.semaphores module parameter is now read-only. Signed-off-by: Chris Wilson Reviewed-by: Dave Gordon --- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- drivers/gpu/drm/i915/i915_dma.c | 2 +- drivers/gpu/drm/i915/i915_drv.c | 25 ----------------------- drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/i915_gem.c | 35 ++++++++++++++++++++++++++++++--- drivers/gpu/drm/i915/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 20 +++++++++---------- 8 files changed, 46 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 5335072f2047..387ae77d3c29 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -3146,7 +3146,7 @@ static int i915_semaphore_status(struct seq_file *m, void *unused) int num_rings = hweight32(INTEL_INFO(dev)->ring_mask); int i, j, ret; - if (!i915_semaphore_is_enabled(dev)) { + if (!i915.semaphores) { seq_puts(m, "Semaphores are disabled\n"); return 0; } diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 9e49e304dd8e..4c72c83cfa28 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -126,7 +126,7 @@ static int i915_getparam(struct drm_device *dev, void *data, value = 1; break; case I915_PARAM_HAS_SEMAPHORES: - value = i915_semaphore_is_enabled(dev); + value = i915.semaphores; break; case I915_PARAM_HAS_PRIME_VMAP_FLUSH: value = 1; diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index e9f85fd0542f..cc831a34f7bb 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -515,31 +515,6 @@ void intel_detect_pch(struct drm_device *dev) pci_dev_put(pch); } -bool i915_semaphore_is_enabled(struct drm_device *dev) -{ - if (INTEL_INFO(dev)->gen < 6) - return false; - - if (i915.semaphores >= 0) - return i915.semaphores; - - /* TODO: make semaphores and Execlists play nicely together */ - if (i915.enable_execlists) - return false; - - /* Until we get further testing... */ - if (IS_GEN8(dev)) - return false; - -#ifdef CONFIG_INTEL_IOMMU - /* Enable semaphores on SNB when IO remapping is off */ - if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) - return false; -#endif - - return true; -} - static void intel_suspend_encoders(struct drm_i915_private *dev_priv) { struct drm_device *dev = dev_priv->dev; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 56cf2ffc1eac..58e9e5e50769 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3226,7 +3226,6 @@ extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, extern void intel_detect_pch(struct drm_device *dev); extern int intel_enable_rc6(const struct drm_device *dev); -extern bool i915_semaphore_is_enabled(struct drm_device *dev); int i915_reg_read_ioctl(struct drm_device *dev, void *data, struct drm_file *file); int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index a4f9c5bbb883..31926a4fb42a 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2567,7 +2567,7 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj, if (i915_gem_request_completed(from_req)) return 0; - if (!i915_semaphore_is_enabled(obj->base.dev)) { + if (!i915.semaphores) { struct drm_i915_private *i915 = to_i915(obj->base.dev); ret = __i915_wait_request(from_req, i915->mm.interruptible, @@ -4304,13 +4304,42 @@ out: return ret; } +static bool i915_gem_sanitize_semaphore(struct drm_i915_private *dev_priv, + int param_value) +{ + if (INTEL_INFO(dev_priv)->gen < 6) + return false; + + if (param_value >= 0) + return param_value; + + /* TODO: make semaphores and Execlists play nicely together */ + if (i915.enable_execlists) + return false; + + /* Until we get further testing... */ + if (IS_GEN8(dev_priv)) + return false; + +#ifdef CONFIG_INTEL_IOMMU + /* Enable semaphores on SNB when IO remapping is off */ + if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped) + return false; +#endif + + return true; +} + int i915_gem_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; int ret; - i915.enable_execlists = intel_sanitize_enable_execlists(dev, - i915.enable_execlists); + i915.enable_execlists = + intel_sanitize_enable_execlists(dev, i915.enable_execlists); + + i915.semaphores = + i915_gem_sanitize_semaphore(dev_priv, i915.semaphores); mutex_lock(&dev->struct_mutex); diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 0aea5ccf6d68..361be1085a18 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -523,7 +523,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) u32 flags = hw_flags | MI_MM_SPACE_GTT; const int num_rings = /* Use an extended w/a on ivb+ if signalling from other rings */ - i915_semaphore_is_enabled(ring->dev) ? + i915.semaphores ? hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 : 0; int len, i, ret; diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 05f054898a95..84ce91275fdd 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -823,7 +823,7 @@ static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv, struct intel_engine_cs *to; int i; - if (!i915_semaphore_is_enabled(dev_priv->dev)) + if (!i915.semaphores) return; if (!error->semaphore_obj) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 02b7032e16e0..e143da96dcfa 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -2510,7 +2510,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev) ring->mmio_base = RENDER_RING_BASE; if (INTEL_INFO(dev)->gen >= 8) { - if (i915_semaphore_is_enabled(dev)) { + if (i915.semaphores) { obj = i915_gem_alloc_object(dev, 4096); if (obj == NULL) { DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); @@ -2534,7 +2534,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev) ring->irq_disable = gen8_ring_disable_irq; ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; ring->irq_seqno_barrier = gen6_seqno_barrier; - if (i915_semaphore_is_enabled(dev)) { + if (i915.semaphores) { WARN_ON(!dev_priv->semaphore_obj); ring->semaphore.sync_to = gen8_ring_sync; ring->semaphore.signal = gen8_rcs_signal; @@ -2550,7 +2550,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev) ring->irq_disable = gen6_ring_disable_irq; ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; ring->irq_seqno_barrier = gen6_seqno_barrier; - if (i915_semaphore_is_enabled(dev)) { + if (i915.semaphores) { ring->semaphore.sync_to = gen6_ring_sync; ring->semaphore.signal = gen6_signal; /* @@ -2666,7 +2666,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) ring->irq_disable = gen8_ring_disable_irq; ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; - if (i915_semaphore_is_enabled(dev)) { + if (i915.semaphores) { ring->semaphore.sync_to = gen8_ring_sync; ring->semaphore.signal = gen8_xcs_signal; GEN8_RING_SEMAPHORE_INIT; @@ -2677,7 +2677,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) ring->irq_disable = gen6_ring_disable_irq; ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; - if (i915_semaphore_is_enabled(dev)) { + if (i915.semaphores) { ring->semaphore.sync_to = gen6_ring_sync; ring->semaphore.signal = gen6_signal; ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; @@ -2734,7 +2734,7 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev) ring->irq_disable = gen8_ring_disable_irq; ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; - if (i915_semaphore_is_enabled(dev)) { + if (i915.semaphores) { ring->semaphore.sync_to = gen8_ring_sync; ring->semaphore.signal = gen8_xcs_signal; GEN8_RING_SEMAPHORE_INIT; @@ -2763,7 +2763,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) ring->irq_enable = gen8_ring_enable_irq; ring->irq_disable = gen8_ring_disable_irq; ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; - if (i915_semaphore_is_enabled(dev)) { + if (i915.semaphores) { ring->semaphore.sync_to = gen8_ring_sync; ring->semaphore.signal = gen8_xcs_signal; GEN8_RING_SEMAPHORE_INIT; @@ -2773,7 +2773,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) ring->irq_enable = gen6_ring_enable_irq; ring->irq_disable = gen6_ring_disable_irq; ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; - if (i915_semaphore_is_enabled(dev)) { + if (i915.semaphores) { ring->semaphore.signal = gen6_signal; ring->semaphore.sync_to = gen6_ring_sync; /* @@ -2820,7 +2820,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev) ring->irq_enable = gen8_ring_enable_irq; ring->irq_disable = gen8_ring_disable_irq; ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; - if (i915_semaphore_is_enabled(dev)) { + if (i915.semaphores) { ring->semaphore.sync_to = gen8_ring_sync; ring->semaphore.signal = gen8_xcs_signal; GEN8_RING_SEMAPHORE_INIT; @@ -2830,7 +2830,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev) ring->irq_enable = hsw_vebox_enable_irq; ring->irq_disable = hsw_vebox_disable_irq; ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; - if (i915_semaphore_is_enabled(dev)) { + if (i915.semaphores) { ring->semaphore.sync_to = gen6_ring_sync; ring->semaphore.signal = gen6_signal; ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;