From patchwork Mon Jan 11 10:44:53 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 8001351 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4EF149F1C0 for ; Mon, 11 Jan 2016 10:47:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 12B9620219 for ; Mon, 11 Jan 2016 10:47:32 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id AFA9820279 for ; Mon, 11 Jan 2016 10:47:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1D02B6E2D6; Mon, 11 Jan 2016 02:47:29 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-f68.google.com (mail-wm0-f68.google.com [74.125.82.68]) by gabe.freedesktop.org (Postfix) with ESMTPS id 24ACD6E2D0 for ; Mon, 11 Jan 2016 02:46:53 -0800 (PST) Received: by mail-wm0-f68.google.com with SMTP id b14so25703233wmb.1 for ; Mon, 11 Jan 2016 02:46:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=1KaM0ZyX95UC/o9Ja5UVYh5PbWX9cAuO6I5pY/2V6Nw=; b=dRfD7XK+M2Z2hd9npoIl8qtEY7VR+G5O3IvME7eQJwYvY9Pba5/GLAFIwtlpPog/Nb P/pz1fRcxUO+SHAnStGe41PNyaENIVCO4MryqtyohocJcGHJtLCC3dwU6q/vy8JqcxhP r3fRkSXujRerZSfq2XQPk9w5WhAt6HH7aXXNeTLiDwqDFRuvLJnRBi7is6VeDp5U9sE3 Jm0/MWzVLy0e+ZoGCeSOu6RxGC/Rpgz2+Y3VtLXb20gS93yaoH4POdzPamLwMDLbEWQE cBmMylDvxL9bA8HLzh0fx33E0jbbdz3bfCbwgErhIms44SA+YWZt85I8ZAsCugnMcjxs F6Jg== X-Received: by 10.194.104.5 with SMTP id ga5mr135241442wjb.155.1452509211864; Mon, 11 Jan 2016 02:46:51 -0800 (PST) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id t3sm118879383wjz.11.2016.01.11.02.46.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 11 Jan 2016 02:46:50 -0800 (PST) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Mon, 11 Jan 2016 10:44:53 +0000 Message-Id: <1452509174-16671-23-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.7.0.rc3 In-Reply-To: <1452509174-16671-1-git-send-email-chris@chris-wilson.co.uk> References: <1452503961-14837-1-git-send-email-chris@chris-wilson.co.uk> <1452509174-16671-1-git-send-email-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 109/190] drm/i915: Remove highly confusing i915_gem_obj_ggtt_pin() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Since i915_gem_obj_ggtt_pin() is an idiom breaking curry function for i915_gem_object_ggtt_pin(), spare us the confustion and remove it. Removing it now simplifies later patches to change the i915_vma_pin() (and friends) interface. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.h | 11 +---------- drivers/gpu/drm/i915/i915_gem.c | 24 ++++++++++-------------- drivers/gpu/drm/i915/i915_gem_context.c | 10 ++++++---- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +- drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +- drivers/gpu/drm/i915/i915_guc_submission.c | 4 ++-- drivers/gpu/drm/i915/intel_guc_loader.c | 2 +- drivers/gpu/drm/i915/intel_lrc.c | 7 ++++--- drivers/gpu/drm/i915/intel_overlay.c | 3 ++- drivers/gpu/drm/i915/intel_ringbuffer.c | 14 ++++++++------ 10 files changed, 36 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f6e508e5aa5b..0e3ff0b24d4d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2713,7 +2713,7 @@ int __must_check i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, const struct i915_ggtt_view *view, uint64_t size, - uint32_t alignment, + uint64_t alignment, uint64_t flags); int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, @@ -2940,15 +2940,6 @@ i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj)); } -static inline int __must_check -i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, - uint32_t alignment, - unsigned flags) -{ - return i915_gem_object_ggtt_pin(obj, &i915_ggtt_view_normal, - 0, alignment, flags); -} - static inline int i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) { diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index c6d7a78ab605..495fb80edee0 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -780,7 +780,9 @@ i915_gem_gtt_pwrite_fast(struct drm_device *dev, char __user *user_data; int page_offset, page_length, ret; - ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); + ret = i915_gem_object_ggtt_pin(obj, NULL, + 0, 0, + PIN_MAPPABLE | PIN_NONBLOCK); if (ret) goto out; @@ -3425,7 +3427,7 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) static bool i915_vma_misplaced(struct i915_vma *vma, uint64_t size, - uint32_t alignment, + uint64_t alignment, uint64_t flags) { struct drm_i915_gem_object *obj = vma->obj; @@ -3521,14 +3523,14 @@ int i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, const struct i915_ggtt_view *view, uint64_t size, - uint32_t alignment, + uint64_t alignment, uint64_t flags) { struct i915_vma *vma; int ret; - if (WARN_ONCE(!view, "no view specified")) - return -EINVAL; + if (view == NULL) + view = &i915_ggtt_view_normal; vma = i915_gem_obj_lookup_or_create_ggtt_vma(obj, view); if (IS_ERR(vma)) @@ -3540,11 +3542,11 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, WARN(vma->pin_count, "bo is already pinned in ggtt with incorrect alignment:" - " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d," + " offset=%08x %08x, req.alignment=%llx, req.map_and_fenceable=%d," " obj->map_and_fenceable=%d\n", upper_32_bits(vma->node.start), lower_32_bits(vma->node.start), - alignment, + (long long)alignment, !!(flags & PIN_MAPPABLE), obj->map_and_fenceable); ret = i915_vma_unbind(vma); @@ -3559,13 +3561,7 @@ void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, const struct i915_ggtt_view *view) { - struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view); - - BUG_ON(!vma); - WARN_ON(vma->pin_count == 0); - WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view)); - - --vma->pin_count; + i915_vma_unpin(i915_gem_obj_to_ggtt_view(obj, view)); } int diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index b7f5781a85ec..15d5a5d247e0 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -378,6 +378,7 @@ int i915_gem_context_init(struct drm_device *dev) } if (ctx->legacy_hw_ctx.rcs_state) { + u32 alignment = get_context_alignment(dev); int ret; /* We may need to do things with the shrinker which @@ -387,8 +388,8 @@ int i915_gem_context_init(struct drm_device *dev) * be available. To avoid this we always pin the default * context. */ - ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state, - get_context_alignment(dev), 0); + ret = i915_gem_object_ggtt_pin(ctx->legacy_hw_ctx.rcs_state, + NULL, 0, alignment, 0); if (ret) { DRM_ERROR("Failed to pinned default global context (error %d)\n", ret); @@ -674,8 +675,9 @@ static int do_switch(struct drm_i915_gem_request *req) /* Trying to pin first makes error handling easier. */ if (engine->id == RCS) { - ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state, - get_context_alignment(engine->dev), 0); + u32 alignment = get_context_alignment(engine->dev); + ret = i915_gem_object_ggtt_pin(to->legacy_hw_ctx.rcs_state, + NULL, 0, alignment, 0); if (ret) return ret; } diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index d4dcc3e5d080..be90d907f890 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1249,7 +1249,7 @@ i915_gem_execbuffer_parse(struct intel_engine_cs *ring, if (ret) goto err; - ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 0, 0); + ret = i915_gem_object_ggtt_pin(shadow_batch_obj, NULL, 0, 0, 0); if (ret) goto err; diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c index 68054f5c4ab1..830c0d24b11e 100644 --- a/drivers/gpu/drm/i915/i915_gem_render_state.c +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c @@ -70,7 +70,7 @@ static int render_state_init(struct render_state *so, struct drm_device *dev) if (so->obj == NULL) return -ENOMEM; - ret = i915_gem_obj_ggtt_pin(so->obj, 4096, 0); + ret = i915_gem_object_ggtt_pin(so->obj, NULL, 0, 0, 0); if (ret) goto free_gem; diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index 63e58253280b..c4d8c34092a9 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -626,8 +626,8 @@ static struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev, return NULL; } - if (i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, - PIN_OFFSET_BIAS | GUC_WOPCM_TOP)) { + if (i915_gem_object_ggtt_pin(obj, NULL, 0, PAGE_SIZE, + PIN_OFFSET_BIAS | GUC_WOPCM_TOP)) { drm_gem_object_unreference(&obj->base); return NULL; } diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index d20788ffd341..dded672d5599 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -296,7 +296,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv) return ret; } - ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0); + ret = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0, 0, 0); if (ret) { DRM_DEBUG_DRIVER("pin failed %d\n", ret); return ret; diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 4d5196547e78..86fa41770ff1 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -581,8 +581,9 @@ static int intel_lr_context_pin(struct intel_context *ctx, lockdep_assert_held(&engine->dev->struct_mutex); ctx_obj = ctx->engine[engine->id].state; - ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, - PIN_OFFSET_BIAS | GUC_WOPCM_TOP); + ret = i915_gem_object_ggtt_pin(ctx_obj, NULL, + 0, GEN8_LR_CONTEXT_ALIGN, + PIN_OFFSET_BIAS | GUC_WOPCM_TOP); if (ret) goto err; @@ -933,7 +934,7 @@ static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size) return -ENOMEM; } - ret = i915_gem_obj_ggtt_pin(ring->wa_ctx.obj, PAGE_SIZE, 0); + ret = i915_gem_object_ggtt_pin(ring->wa_ctx.obj, NULL, 0, PAGE_SIZE, 0); if (ret) { DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n", ret); diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index 094ea87bf6be..414a321b752f 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -1406,7 +1406,8 @@ void intel_setup_overlay(struct drm_device *dev) } overlay->flip_addr = reg_bo->phys_handle->busaddr; } else { - ret = i915_gem_obj_ggtt_pin(reg_bo, PAGE_SIZE, PIN_MAPPABLE); + ret = i915_gem_object_ggtt_pin(reg_bo, NULL, + 0, PAGE_SIZE, PIN_MAPPABLE); if (ret) { DRM_ERROR("failed to pin overlay register bo\n"); goto out_free_bo; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 09799ce72212..ba3631d216fe 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -649,7 +649,7 @@ intel_init_pipe_control(struct intel_engine_cs *ring) if (ret) goto err_unref; - ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0); + ret = i915_gem_object_ggtt_pin(ring->scratch.obj, NULL, 0, 4096, 0); if (ret) goto err_unref; @@ -1848,7 +1848,7 @@ static int init_status_page(struct intel_engine_cs *ring) * actualy map it). */ flags |= PIN_MAPPABLE; - ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); + ret = i915_gem_object_ggtt_pin(obj, NULL, 0, 4096, flags); if (ret) { err_unref: drm_gem_object_unreference(&obj->base); @@ -1891,7 +1891,7 @@ int intel_ring_map(struct intel_ring *ring) int ret; if (HAS_LLC(ring->engine->i915) && !obj->stolen) { - ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, 0); + ret = i915_gem_object_ggtt_pin(obj, NULL, 0, PAGE_SIZE, 0); if (ret) return ret; @@ -1906,7 +1906,8 @@ int intel_ring_map(struct intel_ring *ring) goto unpin; } } else { - ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); + ret = i915_gem_object_ggtt_pin(obj, NULL, 0, PAGE_SIZE, + PIN_MAPPABLE); if (ret) return ret; @@ -2503,7 +2504,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev) i915.semaphores = 0; } else { i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); - ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); + ret = i915_gem_object_ggtt_pin(obj, NULL, + 0, 0, 0); if (ret != 0) { drm_gem_object_unreference(&obj->base); DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); @@ -2603,7 +2605,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev) return -ENOMEM; } - ret = i915_gem_obj_ggtt_pin(obj, 0, 0); + ret = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); if (ret != 0) { drm_gem_object_unreference(&obj->base); DRM_ERROR("Failed to ping batch bo\n");