Message ID | 1453132776-22229-1-git-send-email-arun.siluvery@linux.intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On 18/01/2016 16:20, Patchwork wrote: > == Summary == > > Built on 98ee62c2326e0b6881eb0f427895aab745febf6f drm-intel-nightly: 2016y-01m-18d-14h-18m-27s UTC integration manifest > > Test gem_storedw_loop: > Subgroup basic-render: > pass -> DMESG-WARN (skl-i5k-2) UNSTABLE > pass -> DMESG-WARN (skl-i7k-2) UNSTABLE This patch only changes a define that is used only when GuC submission is enabled (which is disabled by default), this dmesg-warn is not related to this patch. regards Arun > Test kms_pipe_crc_basic: > Subgroup read-crc-pipe-b-frame-sequence: > pass -> DMESG-WARN (byt-nuc) > Subgroup suspend-read-crc-pipe-a: > dmesg-warn -> PASS (snb-x220t) > > bdw-nuci7 total:140 pass:131 dwarn:0 dfail:0 fail:0 skip:9 > bdw-ultra total:140 pass:132 dwarn:1 dfail:1 fail:0 skip:6 > bsw-nuc-2 total:143 pass:117 dwarn:2 dfail:0 fail:0 skip:24 > byt-nuc total:143 pass:124 dwarn:4 dfail:0 fail:0 skip:15 > hsw-brixbox total:143 pass:136 dwarn:0 dfail:0 fail:0 skip:7 > hsw-gt2 total:143 pass:139 dwarn:0 dfail:0 fail:0 skip:4 > ilk-hp8440p total:143 pass:102 dwarn:3 dfail:0 fail:0 skip:38 > ivb-t430s total:137 pass:124 dwarn:3 dfail:4 fail:0 skip:6 > skl-i5k-2 total:143 pass:133 dwarn:2 dfail:0 fail:0 skip:8 > skl-i7k-2 total:143 pass:133 dwarn:2 dfail:0 fail:0 skip:8 > snb-dellxps total:143 pass:124 dwarn:5 dfail:0 fail:0 skip:14 > snb-x220t total:143 pass:124 dwarn:5 dfail:0 fail:1 skip:13 > > Results at /archive/results/CI_IGT_test/Patchwork_1214/ > >
On 18/01/2016 16:20, Patchwork wrote: > == Summary == > > Built on 98ee62c2326e0b6881eb0f427895aab745febf6f drm-intel-nightly: 2016y-01m-18d-14h-18m-27s UTC integration manifest > > Test gem_storedw_loop: > Subgroup basic-render: > pass -> DMESG-WARN (skl-i5k-2) UNSTABLE > pass -> DMESG-WARN (skl-i7k-2) UNSTABLE This patch updates a #define which is only relevant in GuC Submission mode (which is disabled by default). This dmesg-warn is because of an existing issue, https://bugs.freedesktop.org/show_bug.cgi?id=93693 > Test kms_pipe_crc_basic: > Subgroup read-crc-pipe-b-frame-sequence: > pass -> DMESG-WARN (byt-nuc) This is because of https://bugs.freedesktop.org/show_bug.cgi?id=93121 regards Arun > Subgroup suspend-read-crc-pipe-a: > dmesg-warn -> PASS (snb-x220t) > > bdw-nuci7 total:140 pass:131 dwarn:0 dfail:0 fail:0 skip:9 > bdw-ultra total:140 pass:132 dwarn:1 dfail:1 fail:0 skip:6 > bsw-nuc-2 total:143 pass:117 dwarn:2 dfail:0 fail:0 skip:24 > byt-nuc total:143 pass:124 dwarn:4 dfail:0 fail:0 skip:15 > hsw-brixbox total:143 pass:136 dwarn:0 dfail:0 fail:0 skip:7 > hsw-gt2 total:143 pass:139 dwarn:0 dfail:0 fail:0 skip:4 > ilk-hp8440p total:143 pass:102 dwarn:3 dfail:0 fail:0 skip:38 > ivb-t430s total:137 pass:124 dwarn:3 dfail:4 fail:0 skip:6 > skl-i5k-2 total:143 pass:133 dwarn:2 dfail:0 fail:0 skip:8 > skl-i7k-2 total:143 pass:133 dwarn:2 dfail:0 fail:0 skip:8 > snb-dellxps total:143 pass:124 dwarn:5 dfail:0 fail:0 skip:14 > snb-x220t total:143 pass:124 dwarn:5 dfail:0 fail:1 skip:13 > > Results at /archive/results/CI_IGT_test/Patchwork_1214/ > >
Thanks for capture the typo. LGTM. Reviewed-by: Alex Dai <yu.dai@intel.com> On 01/18/2016 07:59 AM, Arun Siluvery wrote: > In GuC submission mode, driver has to provide a list of registers to be > save/restored during gpu reset, make the max no. of registers value consistent > with that of the value defined in FW. If they are not in sync then register > save/restore during gpu reset won't work as expected. > > Cc: Alex Dai <yu.dai@intel.com> > Cc: Dave Gordon <david.s.gordon@intel.com> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h > index 130d94c..1d8048b 100644 > --- a/drivers/gpu/drm/i915/intel_guc_fwif.h > +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h > @@ -370,7 +370,7 @@ struct guc_policies { > #define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8 > #define GUC_REGSET_SAVE_CURRENT_VALUE 0x10 > > -#define GUC_REGSET_MAX_REGISTERS 20 > +#define GUC_REGSET_MAX_REGISTERS 25 > #define GUC_MMIO_WHITE_LIST_START 0x24d0 > #define GUC_MMIO_WHITE_LIST_MAX 12 > #define GUC_S3_SAVE_SPACE_PAGES 10
On Tue, Jan 19, 2016 at 10:13:43AM -0800, Yu Dai wrote: > Thanks for capture the typo. LGTM. > > Reviewed-by: Alex Dai <yu.dai@intel.com> > > On 01/18/2016 07:59 AM, Arun Siluvery wrote: > >In GuC submission mode, driver has to provide a list of registers to be > >save/restored during gpu reset, make the max no. of registers value consistent > >with that of the value defined in FW. If they are not in sync then register > >save/restore during gpu reset won't work as expected. > > > >Cc: Alex Dai <yu.dai@intel.com> > >Cc: Dave Gordon <david.s.gordon@intel.com> > >Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Queued for -next, thanks for the patch. -Daniel > >--- > > drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > >diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h > >index 130d94c..1d8048b 100644 > >--- a/drivers/gpu/drm/i915/intel_guc_fwif.h > >+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h > >@@ -370,7 +370,7 @@ struct guc_policies { > > #define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8 > > #define GUC_REGSET_SAVE_CURRENT_VALUE 0x10 > >-#define GUC_REGSET_MAX_REGISTERS 20 > >+#define GUC_REGSET_MAX_REGISTERS 25 > > #define GUC_MMIO_WHITE_LIST_START 0x24d0 > > #define GUC_MMIO_WHITE_LIST_MAX 12 > > #define GUC_S3_SAVE_SPACE_PAGES 10 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index 130d94c..1d8048b 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -370,7 +370,7 @@ struct guc_policies { #define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8 #define GUC_REGSET_SAVE_CURRENT_VALUE 0x10 -#define GUC_REGSET_MAX_REGISTERS 20 +#define GUC_REGSET_MAX_REGISTERS 25 #define GUC_MMIO_WHITE_LIST_START 0x24d0 #define GUC_MMIO_WHITE_LIST_MAX 12 #define GUC_S3_SAVE_SPACE_PAGES 10
In GuC submission mode, driver has to provide a list of registers to be save/restored during gpu reset, make the max no. of registers value consistent with that of the value defined in FW. If they are not in sync then register save/restore during gpu reset won't work as expected. Cc: Alex Dai <yu.dai@intel.com> Cc: Dave Gordon <david.s.gordon@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> --- drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)