From patchwork Wed Jan 20 19:05:30 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 8073761 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 05B05BEEE5 for ; Wed, 20 Jan 2016 19:06:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 21A55204FC for ; Wed, 20 Jan 2016 19:06:23 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 6A90D20528 for ; Wed, 20 Jan 2016 19:06:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1A22C6E175; Wed, 20 Jan 2016 11:06:20 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E7F46E9DC for ; Wed, 20 Jan 2016 11:06:08 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 20 Jan 2016 11:06:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,322,1449561600"; d="scan'208";a="894834318" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga002.jf.intel.com with SMTP; 20 Jan 2016 11:06:06 -0800 Received: by stinkbox (sSMTP sendmail emulation); Wed, 20 Jan 2016 21:06:05 +0200 From: ville.syrjala@linux.intel.com To: intel-gfx@lists.freedesktop.org Date: Wed, 20 Jan 2016 21:05:30 +0200 Message-Id: <1453316739-13296-10-git-send-email-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.4.10 In-Reply-To: <1453316739-13296-1-git-send-email-ville.syrjala@linux.intel.com> References: <1453316739-13296-1-git-send-email-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 09/18] drm/i915: Support for extra alignment for tiled surfaces X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ville Syrjälä SKL+ needs >4K alignment for tiled surfaces, so make intel_compute_page_offset() handle it. The way we do it is first we compute the closest tile boundary as before, and then figure out how many tiles we need to go to reach the desired alignment. The difference in the offset is then added into the x/y offsets. v2: Be less confusing wrt. units (pixels vs. bytes) (Daniel) Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 47 ++++++++++++++++++++++++++++++++---- 1 file changed, 42 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index bda3224021b2..a102fabce5b4 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2459,6 +2459,35 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb, } /* + * Adjust the tile offset by moving the difference into + * the x/y offsets. + * + * Input tile dimensions and pitch must already be + * rotated to match x and y, and in pixel units. + */ +static void intel_adjust_tile_offset(int *x, int *y, + unsigned int tile_width, + unsigned int tile_height, + unsigned int tile_size, + unsigned int pitch_tiles, + unsigned int old_offset, + unsigned int new_offset) +{ + unsigned int tiles; + + WARN_ON(old_offset & (tile_size - 1)); + WARN_ON(new_offset & (tile_size - 1)); + WARN_ON(new_offset > old_offset); + + tiles = (old_offset - new_offset) / tile_size; + if (tiles == 0) + return; + + *y += tiles / pitch_tiles * tile_height; + *x += tiles % pitch_tiles * tile_width; +} + +/* * Computes the linear offset to the base tile and adjusts * x, y. bytes per pixel is assumed to be a power-of-two. * @@ -2473,6 +2502,12 @@ u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv, unsigned int pitch, unsigned int rotation) { + unsigned int offset, alignment; + + alignment = intel_surf_alignment(dev_priv, fb_modifier); + if (alignment) + alignment--; + if (fb_modifier != DRM_FORMAT_MOD_NONE) { unsigned int tile_size, tile_width, tile_height; unsigned int tile_rows, tiles, pitch_tiles; @@ -2494,16 +2529,18 @@ u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv, tiles = *x / tile_width; *x %= tile_width; - return (tile_rows * pitch_tiles + tiles) * tile_size; - } else { - unsigned int alignment = intel_linear_alignment(dev_priv) - 1; - unsigned int offset; + offset = (tile_rows * pitch_tiles + tiles) * tile_size; + intel_adjust_tile_offset(x, y, tile_width, tile_height, + tile_size, pitch_tiles, + offset, offset & ~alignment); + } else { offset = *y * pitch + *x * cpp; *y = (offset & alignment) / pitch; *x = ((offset & alignment) - *y * pitch) / cpp; - return offset & ~alignment; } + + return offset & ~alignment; } static int i9xx_format_to_fourcc(int format)