From patchwork Thu Jan 21 02:26:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tom.orourke@intel.com X-Patchwork-Id: 8076951 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B0F349F1C0 for ; Thu, 21 Jan 2016 02:28:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A6BA5205E8 for ; Thu, 21 Jan 2016 02:28:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id B1167205E7 for ; Thu, 21 Jan 2016 02:28:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D01D772112; Wed, 20 Jan 2016 18:28:00 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 3969B72110 for ; Wed, 20 Jan 2016 18:27:34 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP; 20 Jan 2016 18:27:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,323,1449561600"; d="scan'208";a="897780528" Received: from torourke-desk.ra.intel.com (HELO localhost.localdomain) ([10.10.35.157]) by fmsmga002.fm.intel.com with ESMTP; 20 Jan 2016 18:27:33 -0800 From: tom.orourke@intel.com To: intel-gfx@lists.freedesktop.org Date: Wed, 20 Jan 2016 18:26:21 -0800 Message-Id: <1453343184-160456-20-git-send-email-tom.orourke@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1453343184-160456-1-git-send-email-tom.orourke@intel.com> References: <1453343184-160456-1-git-send-email-tom.orourke@intel.com> Cc: Tom O'Rourke Subject: [Intel-gfx] [RFC 19/22] drm/i915/slpc: Add parameter unset/set/get functions X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Tom O'Rourke Add slcp_param_id enum values. Add events for setting/unsetting parameters. Signed-off-by: Tom O'Rourke --- drivers/gpu/drm/i915/intel_slpc.c | 127 ++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_slpc.h | 22 +++++++ 2 files changed, 149 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c index 36aedb9..3abaf0b 100644 --- a/drivers/gpu/drm/i915/intel_slpc.c +++ b/drivers/gpu/drm/i915/intel_slpc.c @@ -119,6 +119,47 @@ static int host2guc_slpc_query_task_state(struct drm_i915_private *dev_priv) return ret; } +static int host2guc_slpc_set_param(struct drm_i915_private *dev_priv, + enum slpc_param_id id, u32 value) +{ + u32 data[4]; + int ret; + + data[0] = HOST2GUC_ACTION_SLPC_REQUEST; + data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2); + data[2] = (u32) id; + data[3] = value; + + ret = host2guc_action(&dev_priv->guc, data, 4); + + if (0 == ret) { + ret = I915_READ(SOFT_SCRATCH(1)); + ret &= 0xFF; + } + + return ret; +} + +static int host2guc_slpc_unset_param(struct drm_i915_private *dev_priv, + enum slpc_param_id id) +{ + u32 data[3]; + int ret; + + data[0] = HOST2GUC_ACTION_SLPC_REQUEST; + data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1); + data[2] = (u32) id; + + ret = host2guc_action(&dev_priv->guc, data, 3); + + if (0 == ret) { + ret = I915_READ(SOFT_SCRATCH(1)); + ret &= 0xFF; + } + + return ret; +} + static u8 slpc_get_platform_sku(struct drm_i915_gem_object *obj) { struct drm_device *dev = obj->base.dev; @@ -370,3 +411,89 @@ int intel_slpc_query_task_state(struct drm_device *dev) return host2guc_slpc_query_task_state(dev_priv); } + +int intel_slpc_unset_param(struct drm_device *dev, enum slpc_param_id id) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_i915_gem_object *obj; + struct page *page; + struct slpc_shared_data *data = NULL; + int ret = 0; + + obj = dev_priv->guc.slpc.shared_data_obj; + if (obj) { + page = i915_gem_object_get_page(obj, 0); + if (page) + data = kmap_atomic(page); + } + + if (data) { + data->override_parameters_set_bits[id >> 5] + &= (~(1 << (id % 32))); + data->override_parameters_values[id] = 0; + kunmap_atomic(data); + + ret = host2guc_slpc_unset_param(dev_priv, id); + } + + return ret; +} + +int intel_slpc_set_param(struct drm_device *dev, enum slpc_param_id id, + u32 value) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_i915_gem_object *obj; + struct page *page; + struct slpc_shared_data *data = NULL; + int ret = 0; + + obj = dev_priv->guc.slpc.shared_data_obj; + if (obj) { + page = i915_gem_object_get_page(obj, 0); + if (page) + data = kmap_atomic(page); + } + + if (data) { + data->override_parameters_set_bits[id >> 5] + |= (1 << (id % 32)); + data->override_parameters_values[id] = value; + kunmap_atomic(data); + + ret = host2guc_slpc_set_param(dev_priv, id, value); + } + + return ret; +} + +int intel_slpc_get_param(struct drm_device *dev, enum slpc_param_id id, + int *overriding, u32 *value) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_i915_gem_object *obj; + struct page *page; + struct slpc_shared_data *data = NULL; + u32 bits; + int ret = 0; + + obj = dev_priv->guc.slpc.shared_data_obj; + if (obj) { + page = i915_gem_object_get_page(obj, 0); + if (page) + data = kmap_atomic(page); + } + + if (data) { + if (overriding) { + bits = data->override_parameters_set_bits[id >> 5]; + *overriding = (0 != (bits & (1 << (id % 32)))); + } + if (value) + *value = data->override_parameters_values[id]; + + kunmap_atomic(data); + } + + return ret; +} diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h index 32d7dcc..fc74ce3 100644 --- a/drivers/gpu/drm/i915/intel_slpc.h +++ b/drivers/gpu/drm/i915/intel_slpc.h @@ -68,6 +68,23 @@ enum slpc_event_id { #define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc)) +enum slpc_param_id { + SLPC_PARAM_TASK_ENABLE_DFPS = 2, + SLPC_PARAM_TASK_DISABLE_DFPS = 3, + SLPC_PARAM_TASK_ENABLE_TURBO = 4, + SLPC_PARAM_TASK_DISABLE_TURBO = 5, + SLPC_PARAM_TASK_ENABLE_DCC = 6, + SLPC_PARAM_TASK_DISABLE_DCC = 7, + SLPC_PARAM_GLOBAL_MIN_GT_FREQ_MHZ = 8, + SLPC_PARAM_GLOBAL_MAX_GT_FREQ_MHZ = 9, + SLPC_PARAM_DFPS_THRESHOLD_MAX_FPS = 10, + SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11, + SLPC_PARAM_DFPS_DISABLE_FRAMERATE_STALLING = 12, + SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13, + SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14, + SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15, +}; + enum slpc_global_state { SLPC_GLOBAL_STATE_NOT_RUNNING = 0, SLPC_GLOBAL_STATE_INITIALIZING = 1, @@ -182,4 +199,9 @@ int intel_slpc_update_display_mode_info(struct drm_device *dev); int intel_slpc_update_display_rr_info(struct drm_device *dev, u32 refresh_rate); int intel_slpc_query_task_state(struct drm_device *dev); +int intel_slpc_unset_param(struct drm_device *dev, enum slpc_param_id id); +int intel_slpc_set_param(struct drm_device *dev, enum slpc_param_id id, + u32 value); +int intel_slpc_get_param(struct drm_device *dev, enum slpc_param_id id, + int *overriding, u32 *value); #endif