@@ -5118,6 +5118,9 @@ i915_max_freq_set(void *data, u64 val)
}
dev_priv->rps.max_freq_softlimit = val;
+ if (HAS_SLPC(dev))
+ intel_slpc_set_param(dev, SLPC_PARAM_GLOBAL_MAX_GT_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
intel_set_rps(dev, val);
@@ -5185,6 +5188,9 @@ i915_min_freq_set(void *data, u64 val)
}
dev_priv->rps.min_freq_softlimit = val;
+ if (HAS_SLPC(dev))
+ intel_slpc_set_param(dev, SLPC_PARAM_GLOBAL_MIN_GT_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
intel_set_rps(dev, val);
@@ -389,6 +389,10 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
dev_priv->rps.max_freq_softlimit = val;
+ if (HAS_SLPC(dev))
+ intel_slpc_set_param(dev, SLPC_PARAM_GLOBAL_MAX_GT_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+
val = clamp_t(int, dev_priv->rps.cur_freq,
dev_priv->rps.min_freq_softlimit,
dev_priv->rps.max_freq_softlimit);
@@ -448,6 +452,10 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
dev_priv->rps.min_freq_softlimit = val;
+ if (HAS_SLPC(dev))
+ intel_slpc_set_param(dev, SLPC_PARAM_GLOBAL_MIN_GT_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+
val = clamp_t(int, dev_priv->rps.cur_freq,
dev_priv->rps.min_freq_softlimit,
dev_priv->rps.max_freq_softlimit);