From patchwork Thu Jan 21 19:37:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Gordon X-Patchwork-Id: 8084641 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id AC255BEEE5 for ; Thu, 21 Jan 2016 19:37:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B38A020395 for ; Thu, 21 Jan 2016 19:37:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id B15C220389 for ; Thu, 21 Jan 2016 19:37:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A53706E5E6; Thu, 21 Jan 2016 11:37:54 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id EFE416E5E8 for ; Thu, 21 Jan 2016 11:37:52 -0800 (PST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP; 21 Jan 2016 11:37:53 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,326,1449561600"; d="scan'208";a="638000987" Received: from dsgordon-linux2.isw.intel.com ([10.102.226.88]) by FMSMGA003.fm.intel.com with ESMTP; 21 Jan 2016 11:37:51 -0800 From: Dave Gordon To: intel-gfx@lists.freedesktop.org Date: Thu, 21 Jan 2016 19:37:44 +0000 Message-Id: <1453405067-32890-2-git-send-email-david.s.gordon@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1453405067-32890-1-git-send-email-david.s.gordon@intel.com> References: <1453405067-32890-1-git-send-email-david.s.gordon@intel.com> Organization: Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ Subject: [Intel-gfx] [PATCH 1/4] drm/i915: handle teardown of HWSP when context is freed X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Existing code did a kunmap() on the wrong page, and didn't account for the fact that the HWSP and the default context are different offsets within the same GEM object. This patch improves symmetry by creating lrc_teardown_hardware_status_page() to complement lrc_setup_hardware_status_page(), making sure that they both take the same argument (pointer to engine). They encapsulate all the details of the relationship between the default context and the status page, so the rest of the LRC code doesn't have to know about it. Signed-off-by: Dave Gordon --- drivers/gpu/drm/i915/intel_lrc.c | 57 ++++++++++++++++++++++++++++------------ 1 file changed, 40 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 73d4347..3914120 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -226,9 +226,8 @@ enum { #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 static int intel_lr_context_pin(struct drm_i915_gem_request *rq); -static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring, - struct drm_i915_gem_object *default_ctx_obj); - +static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring); +static void lrc_teardown_hardware_status_page(struct intel_engine_cs *ring); /** * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists @@ -1536,8 +1535,7 @@ static int gen8_init_common_ring(struct intel_engine_cs *ring) struct drm_i915_private *dev_priv = dev->dev_private; u8 next_context_status_buffer_hw; - lrc_setup_hardware_status_page(ring, - dev_priv->kernel_context->engine[ring->id].state); + lrc_setup_hardware_status_page(ring); I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); @@ -1992,10 +1990,9 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *ring) i915_cmd_parser_fini_ring(ring); i915_gem_batch_pool_fini(&ring->batch_pool); - if (ring->status_page.obj) { - kunmap(sg_page(ring->status_page.obj->pages->sgl)); - ring->status_page.obj = NULL; - } + /* Status page should have gone already */ + WARN_ON(ring->status_page.page_addr); + WARN_ON(ring->status_page.obj); ring->disable_lite_restore_wa = false; ring->ctx_desc_template = 0; @@ -2434,6 +2431,11 @@ void intel_lr_context_free(struct intel_context *ctx) continue; if (ctx == ctx->i915->kernel_context) { + /* + * The HWSP is part of the default context + * object in LRC mode. + */ + lrc_teardown_hardware_status_page(ringbuf->ring); intel_unpin_ringbuffer_obj(ringbuf); i915_gem_object_ggtt_unpin(ctx_obj); } @@ -2482,24 +2484,45 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *ring) return ret; } -static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring, - struct drm_i915_gem_object *default_ctx_obj) +static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring) { - struct drm_i915_private *dev_priv = ring->dev->dev_private; + struct drm_i915_private *dev_priv = to_i915(ring->dev); + struct intel_context *dctx = dev_priv->kernel_context; + struct drm_i915_gem_object *dctx_obj = dctx->engine[ring->id].state; + u64 dctx_addr = i915_gem_obj_ggtt_offset(dctx_obj); struct page *page; - /* The HWSP is part of the default context object in LRC mode. */ - ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj) - + LRC_PPHWSP_PN * PAGE_SIZE; - page = i915_gem_object_get_page(default_ctx_obj, LRC_PPHWSP_PN); + /* + * The HWSP is part of the default context object in LRC mode. + * Note that it doesn't contribute to the refcount! + */ + page = i915_gem_object_get_page(dctx_obj, LRC_PPHWSP_PN); ring->status_page.page_addr = kmap(page); - ring->status_page.obj = default_ctx_obj; + ring->status_page.gfx_addr = dctx_addr + LRC_PPHWSP_PN * PAGE_SIZE; + ring->status_page.obj = dctx_obj; I915_WRITE(RING_HWS_PGA(ring->mmio_base), (u32)ring->status_page.gfx_addr); POSTING_READ(RING_HWS_PGA(ring->mmio_base)); } +/* This should be called before the default context is destroyed */ +static void lrc_teardown_hardware_status_page(struct intel_engine_cs *ring) +{ + struct drm_i915_gem_object *dctx_obj = ring->status_page.obj; + struct page *page; + + WARN_ON(!dctx_obj); + + if (ring->status_page.page_addr) { + page = i915_gem_object_get_page(dctx_obj, LRC_PPHWSP_PN); + kunmap(page); + ring->status_page.page_addr = NULL; + } + + ring->status_page.obj = NULL; +} + /** * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context * @ctx: LR context to create.