From patchwork Wed Jan 27 16:10:03 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Shobhit" X-Patchwork-Id: 8135331 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 10E14BEEE5 for ; Wed, 27 Jan 2016 16:10:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 513B220270 for ; Wed, 27 Jan 2016 16:10:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 2AC2620221 for ; Wed, 27 Jan 2016 16:10:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 887D96E711; Wed, 27 Jan 2016 08:10:54 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id D79EB6E711 for ; Wed, 27 Jan 2016 08:10:53 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP; 27 Jan 2016 08:10:26 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,355,1449561600"; d="scan'208";a="902256338" Received: from skumar40-mobl.iind.intel.com ([10.223.179.230]) by fmsmga002.fm.intel.com with ESMTP; 27 Jan 2016 08:10:20 -0800 From: Shobhit Kumar To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jan 2016 21:40:03 +0530 Message-Id: <1453911003-9856-6-git-send-email-shobhit.kumar@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1453911003-9856-1-git-send-email-shobhit.kumar@intel.com> References: <1453911003-9856-1-git-send-email-shobhit.kumar@intel.com> Subject: [Intel-gfx] [v2 6/6] drm/i915/skl: WA for watermark calculation based on Arbitrated Display BW X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Kumar, Mahesh" If the arbitary display bandwidth is > 60% of memory bandwith, for x-tile we should increase latency at all levels by 15us. If the arbitary dsplay bandwidth is greater than 20% of memory bandwith in case of y-tile being enabled, double the scan lines v2: Update the commit message to explain the WA (shobhit) v3: - Address Damien's comment, use DIV_ROUND_UP_ULL macro - Check both mem_speed and mem_channel to be valid before applying WA(shobhit) Signed-off-by: Shobhit Kumar Signed-off-by: Kumar, Mahesh Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/i915_drv.h | 9 ++++ drivers/gpu/drm/i915/intel_pm.c | 92 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b040e7a..450e6d3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1624,6 +1624,12 @@ enum intel_pipe_crc_source { INTEL_PIPE_CRC_SOURCE_MAX, }; +enum watermark_memory_wa { + WATERMARK_WA_NONE, + WATERMARK_WA_X_TILED, + WATERMARK_WA_Y_TILED, +}; + struct intel_pipe_crc_entry { uint32_t frame; uint32_t crc[5]; @@ -1926,6 +1932,9 @@ struct drm_i915_private { /* Committed wm config */ struct intel_wm_config config; + /* This stores if WaterMark memory workaround is needed */ + enum watermark_memory_wa mem_wa; + /* * The skl_wm_values structure is a bit too big for stack * allocation, so we keep the staging struct where we store diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a9f9396..da5ff34 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3225,6 +3225,11 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, if (latency == 0 || !cstate->base.active || !intel_pstate->visible) return false; + if (dev_priv->wm.mem_wa != WATERMARK_WA_NONE) { + if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) + latency += 15; + } + width = drm_rect_width(&intel_pstate->src) >> 16; height = drm_rect_height(&intel_pstate->src) >> 16; @@ -3265,6 +3270,9 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, WARN(1, "Unsupported pixel depth for rotation"); } } + if (dev_priv->wm.mem_wa == WATERMARK_WA_Y_TILED) + min_scanlines *= 2; + y_tile_minimum = plane_blocks_per_line * min_scanlines; selected_result = max(method2, y_tile_minimum); } else { @@ -3715,6 +3723,89 @@ static void skl_set_plane_pixel_rate(struct drm_crtc *crtc) } +static void +skl_set_display_memory_wa(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = NULL; + struct intel_plane *intel_plane = NULL; + uint32_t num_active_crtc = 0; + uint64_t max_pixel_rate_pipe = 0; + uint64_t display_bw = 0, available_bw = 0; + bool y_tile_enabled = false; + int memory_portion = 0; + + /* Verify that we got proper memory information */ + if (dev_priv->dmi.mem_channel == 0 || dev_priv->dmi.mem_speed == -1) { + dev_priv->wm.mem_wa = WATERMARK_WA_NONE; + return; + } + + for_each_intel_crtc(dev, intel_crtc) { + uint64_t max_pixel_rate_plane = 0; + uint64_t pipe_bw; + uint32_t num_active_plane = 0; + const struct intel_crtc_state *cstate = NULL; + + if (!intel_crtc->active) + continue; + cstate = to_intel_crtc_state(intel_crtc->base.state); + num_active_crtc++; + + for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { + struct drm_plane *plane = &intel_plane->base; + struct drm_framebuffer *fb = plane->state->fb; + uint64_t plane_bw, interm_bw = 10000000; + + if (fb == NULL) + continue; + if (plane->type == DRM_PLANE_TYPE_CURSOR) + continue; + num_active_plane++; + + if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED) + y_tile_enabled = true; + + /* + * planeBW = pixel_rate(MHz) * BPP * plane downscale + * amount * pipe downscale amount; + * + * skl_pipe_pixel_rate return adjusted value according + * to downscaling amount + * pixel rate is in KHz & downscale factor is multiplied + * by 1000, so devide by 1000*1000 + */ + interm_bw = skl_pipe_pixel_rate(cstate) * + drm_format_plane_cpp(fb->pixel_format, 0) * + skl_plane_downscale_amount(intel_plane); + + if (fb->pixel_format == DRM_FORMAT_NV12) + interm_bw += skl_pipe_pixel_rate(cstate) * + drm_format_plane_cpp(fb->pixel_format, 1) * + skl_plane_downscale_amount(intel_plane); + + plane_bw = DIV_ROUND_UP(interm_bw, (uint64_t) (1000 * + 1000)); + max_pixel_rate_plane = max(max_pixel_rate_plane, + plane_bw); + } + pipe_bw = max_pixel_rate_plane * num_active_plane; + max_pixel_rate_pipe = max(max_pixel_rate_pipe, pipe_bw); + } + display_bw = max_pixel_rate_pipe * num_active_crtc; + + available_bw = dev_priv->dmi.mem_channel * dev_priv->dmi.mem_speed * 8; + + memory_portion = DIV_ROUND_UP_ULL((display_bw * 100), available_bw); + + if (y_tile_enabled && (memory_portion >= 20)) + dev_priv->wm.mem_wa = WATERMARK_WA_Y_TILED; + else if (memory_portion >= 60) + dev_priv->wm.mem_wa = WATERMARK_WA_X_TILED; + else + dev_priv->wm.mem_wa = WATERMARK_WA_NONE; +} + static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe) { watermarks->wm_linetime[pipe] = 0; @@ -3752,6 +3843,7 @@ static void skl_update_wm(struct drm_crtc *crtc) /* Calculate plane pixel rate for each plane in advance */ skl_set_plane_pixel_rate(crtc); + skl_set_display_memory_wa(dev); if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm)) return;