From patchwork Thu Jan 28 10:21:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Zhi A" X-Patchwork-Id: 8148441 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E0D059F440 for ; Thu, 28 Jan 2016 10:23:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EF80020218 for ; Thu, 28 Jan 2016 10:23:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id C304F2034C for ; Thu, 28 Jan 2016 10:23:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5CD0F6E7EE; Thu, 28 Jan 2016 02:23:53 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 9ECE66E7ED for ; Thu, 28 Jan 2016 02:23:49 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP; 28 Jan 2016 02:23:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,358,1449561600"; d="scan'208";a="870587698" Received: from dev-inno.bj.intel.com ([10.238.135.69]) by orsmga001.jf.intel.com with ESMTP; 28 Jan 2016 02:23:46 -0800 From: Zhi Wang To: intel-gfx@lists.freedesktop.org, igvt-g@lists.01.org Date: Thu, 28 Jan 2016 18:21:25 +0800 Message-Id: <1453976511-27322-4-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1453976511-27322-1-git-send-email-zhi.a.wang@intel.com> References: <1453976511-27322-1-git-send-email-zhi.a.wang@intel.com> Cc: daniel.vetter@ffwll.ch, david.j.cowperthwaite@intel.com Subject: [Intel-gfx] [RFC 03/29] drm/i915: Introduce GVT context creation API X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP GVT workload scheduler needs special host LRC contexts, the so called "shadow LRC context" to submit guest workload to host i915. During the guest workload submission, GVT fills the shadow LRC context with the content of guest LRC context: engine context is copied without changes, ring context is mostly owned by host i915, except the PPGTT root pointers, which will be filled with the shadow PPGTT page table root pointers managed by GVT-g. The GVT-g workload scheduler flow: +-----------+ +-----------+ | GVT Guest | | GVT Guest | +-+-----^---+ +-+-----^---+ | | | | | | GVT-g | | GVT-g vELSP write| | emulates vELSP write| | emulates | | Execlist/CSB | | Execlist/CSB | | Status | | Status | | | | +------v-----+-------------------------v-----+---------+ | GVT Virtual Execlist Submission | +------+-------------------------------+---------------+ | | | Per-VM/Ring Workoad Q | Per-VM/Ring Workload Q +---------------------+--+ +------------------------+ +---v--------+ ^ +---v--------+ |GVT Workload|... | |GVT Workload|... +------------+ | +------------+ | | Pick Workload from Q +--------------------+---------------------------------+ | GVT Workload Scheduler | +--------------------+---------------------------------+ | * Shadow guest LRC context +------v------+ * Shadow guest ring buffer | GVT Context | * Scan/Patch guest RB instructions +------+------+ | v Host i915 GEM Submission Guest ELSP submission will be wrapped into a GVT workload data structure. When a guest is scheduled, workload scheduler picks the GVT workload from the per-VM/ring Q, then prepare to dispatch it through host i915 GEM submission. The GVT workload lifecycle: - Workload scheduler populates the GVT LRC context with the content of guest LRC context - Workload scheduler populates the GVT ring buffer with the instructions from guest ring buffer - Workload scheduler populates the PDPs in the GVT LRC context with shadow PPGTT PDPs - Workload scheduler submits this context through i915 GEM submission interface - Once the i915 gem request is finished, GVT-g waits until the GVT LRC context is idle. - i915 LRC routines notifies workload scheduler the LRC context is idle. - Workload scheduler updates the guest LRC context with the content of GVT LRC context - Emulate CSB and context switch interrupt to guest Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/i915_drv.h | 20 +++++++++++++++++ drivers/gpu/drm/i915/i915_gem_context.c | 38 +++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index db3c79b..fc5ddee 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -890,6 +890,24 @@ struct intel_context { } engine[I915_NUM_RINGS]; struct list_head link; + + /* Is a GVT context ? */ + bool gvt_context; + /* Used by GVT workload scheduler. */ + void *gvt_context_private_data[I915_NUM_RINGS]; + /* + * As GVT context may comes from different guest, + * the addressing mode may be different + */ + u32 gvt_context_addressing_mode[I915_NUM_RINGS]; + /* + * Called when GVT context is scheduled-in + */ + void (*gvt_context_schedule_in)(void *data); + /* + * Called when GVT context is scheduled-out + */ + void (*gvt_context_schedule_out)(void *data); }; enum fb_op_origin { @@ -2866,6 +2884,8 @@ struct drm_i915_gem_object *i915_gem_object_create_from_data( void i915_gem_free_object(struct drm_gem_object *obj); void i915_gem_vma_destroy(struct i915_vma *vma); +struct intel_context * i915_gem_create_gvt_context(struct drm_device *dev); + /* Flags used by pin/bind&friends. */ #define PIN_MAPPABLE (1<<0) #define PIN_NONBLOCK (1<<1) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 6a4f64b..410540a 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -260,6 +260,44 @@ err_out: return ERR_PTR(ret); } +struct intel_context * +i915_gem_create_gvt_context(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_context *ctx; + int ret; + int i; + + mutex_lock(&dev->struct_mutex); + + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); + if (ctx == NULL) + return ERR_PTR(-ENOMEM); + + kref_init(&ctx->ref); + list_add_tail(&ctx->link, &dev_priv->context_list); + + ctx->i915 = dev_priv; + ctx->file_priv = NULL; + ctx->user_handle = -1; + ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1; + ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD; + + ctx->gvt_context = true; + + for (i = 0; i < I915_NUM_RINGS; i++) { + ret = intel_lr_context_deferred_alloc(ctx, &dev_priv->ring[i]); + if (ret) { + i915_gem_context_unreference(ctx); + ctx = NULL; + goto out; + } + } +out: + mutex_unlock(&dev->struct_mutex); + return ctx; +} + /** * The default context needs to exist per ring that uses contexts. It stores the * context state of the GPU for applications that don't utilize HW contexts, as