From patchwork Mon Feb 8 09:55:46 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 8247441 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2A423BEEE5 for ; Mon, 8 Feb 2016 09:55:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 42BB020259 for ; Mon, 8 Feb 2016 09:55:31 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 66E9B2022A for ; Mon, 8 Feb 2016 09:55:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EB94C6E38A; Mon, 8 Feb 2016 01:55:29 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-f45.google.com (mail-wm0-f45.google.com [74.125.82.45]) by gabe.freedesktop.org (Postfix) with ESMTPS id 019666E38A for ; Mon, 8 Feb 2016 01:55:28 -0800 (PST) Received: by mail-wm0-f45.google.com with SMTP id c200so7153295wme.0 for ; Mon, 08 Feb 2016 01:55:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id; bh=Md27BiXeYDkD9ujJRvYmomsHEQ00soj5Gt8WA6731zM=; b=ENGm0eQVyqb7dxLdUColyUsdlwnIJHPsUyrS8NOjmO+PW7G16oSR0KffJ+bFAEjD1e 6tpI7yc5/SReL0Rv/4hogBaB0oCvvLUgcuSwvC2SbSdQGz5cbdilOQ/7SO6UWQrNcCFW rIbpCg7ULuWNmwh1P5QraVw0iL9p1f/UzwsF0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Md27BiXeYDkD9ujJRvYmomsHEQ00soj5Gt8WA6731zM=; b=B82955JiGbsoJHeTlBbXfpljfRw0si197Rf0FXl+AGGUBx/I8GuTTt5HenEvz5cmWd 0h5NQtewFnjS2/lZxrMkRKBwbfCS6R59v6XzOQBWtiP6uFSR3fV1qc6+O2xwaEASuw7R Xle90ihWrzCetXbYBr+9OKvBxy1i9OFcW4zDo20Q++2DDFAyUoepw5li0BC8iNpZWhe/ Efo6M0J4gd/fCaMOp0Hu+QMUGtfgrlvfUodta4uFszgjxnMtNbArXNJvbALezmgc4xOv jKNkZw9T/CmMIHLwFJs2x+XB20vVwRl8OMxkNw1szeaDk+328f3GLgALcV9RjEiUJ5os aU8w== X-Gm-Message-State: AG10YORqeftmecH+knA4QJnCHNwmrLOjzwcDo0bahzoSCjIbbEUfDwF+hrGe5JObGDGnwA== X-Received: by 10.195.13.129 with SMTP id ey1mr26108085wjd.132.1454925326501; Mon, 08 Feb 2016 01:55:26 -0800 (PST) Received: from phenom.ffwll.local ([2a02:168:56c9:0:22cf:30ff:fe4c:37d6]) by smtp.gmail.com with ESMTPSA id az10sm28959314wjc.28.2016.02.08.01.55.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Feb 2016 01:55:25 -0800 (PST) From: Daniel Vetter To: Intel Graphics Development Date: Mon, 8 Feb 2016 10:55:46 +0100 Message-Id: <1454925346-22479-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 2.7.0.rc3 Cc: Jani Nikula , Daniel Vetter , Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: restrict PP save/restore to platforms with lvds X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP eDP already restores PP state completely on it's own, we only need this code for LVDS. Since it's more work to move this into the lvds encoder properly just limit it to affected pch chips for now (ibx&cpt/ppt). Cc: Jani Nikula Acked-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_suspend.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index a2aa09ce3202..7f6b050266a7 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -43,8 +43,8 @@ static void i915_save_display(struct drm_device *dev) else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) dev_priv->regfile.saveLVDS = I915_READ(LVDS); - /* Panel power sequencer */ - if (HAS_PCH_SPLIT(dev)) { + /* Panel power sequencer, only needed for LVDS */ + if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL); dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); @@ -78,8 +78,8 @@ static void i915_restore_display(struct drm_device *dev) else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask); - /* Panel power sequencer */ - if (HAS_PCH_SPLIT(dev)) { + /* Panel power sequencer, only needed for LVDS */ + if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS); I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);