| Message ID | 1455808874-22089-4-git-send-email-mika.kuoppala@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On to, 2016-02-18 at 17:21 +0200, Mika Kuoppala wrote: > Cores need to be included into the debug mask. We don't exactly > know what it does but the spec says it must be enabled. So obey. > > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_runtime_pm.c | 14 ++++++++------ > 2 files changed, 9 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > index 3774870477c1..f76cbf3e5d1e 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7568,6 +7568,7 @@ enum skl_disp_power_wells { > #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 > > #define DC_STATE_DEBUG _MMIO(0x45520) > +#define DC_STATE_DEBUG_MASK_CORES (1<<0) > #define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1) > > /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using > this register, > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c > b/drivers/gpu/drm/i915/intel_runtime_pm.c > index cb91540cfbad..1b490c7e4020 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -456,15 +456,17 @@ static void assert_can_disable_dc9(struct > drm_i915_private *dev_priv) > */ > } > > -static void gen9_set_dc_state_debugmask_memory_up( > - struct drm_i915_private *dev_priv) > +static void gen9_set_dc_state_debugmask(struct drm_i915_private > *dev_priv) > { > - uint32_t val; > + uint32_t val, mask; > + > + mask = DC_STATE_DEBUG_MASK_MEMORY_UP | > + DC_STATE_DEBUG_MASK_CORES; The BSpec "Sequence to Allow DC5 or DC6" requires this only for BXT (looks like a recent addition to work around something), but it doesn't say it's needed for other platforms. The register description doesn't make a difference though. Perhaps Art has more info on this, adding him. > > /* The below bit doesn't need to be cleared ever afterwards > */ > val = I915_READ(DC_STATE_DEBUG); > - if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) { > - val |= DC_STATE_DEBUG_MASK_MEMORY_UP; > + if ((val & mask) != mask) { > + val |= mask; > I915_WRITE(DC_STATE_DEBUG, val); > POSTING_READ(DC_STATE_DEBUG); > } > @@ -525,7 +527,7 @@ static void gen9_set_dc_state(struct > drm_i915_private *dev_priv, uint32_t state) > state = DC_STATE_EN_UPTO_DC5; > > if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK) > - gen9_set_dc_state_debugmask_memory_up(dev_priv); > + gen9_set_dc_state_debugmask(dev_priv); > > val = I915_READ(DC_STATE_EN); > DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
>-----Original Message----- >From: Deak, Imre ... >The BSpec "Sequence to Allow DC5 or DC6" requires this only for BXT >(looks like a recent addition to work around something), but it doesn't >say it's needed for other platforms. The register description doesn't >make a difference though. > >Perhaps Art has more info on this, adding him. > Only BXT needs it programmed to 1b at the moment. Other products should keep the default.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3774870477c1..f76cbf3e5d1e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7568,6 +7568,7 @@ enum skl_disp_power_wells { #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 #define DC_STATE_DEBUG _MMIO(0x45520) +#define DC_STATE_DEBUG_MASK_CORES (1<<0) #define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1) /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index cb91540cfbad..1b490c7e4020 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -456,15 +456,17 @@ static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) */ } -static void gen9_set_dc_state_debugmask_memory_up( - struct drm_i915_private *dev_priv) +static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) { - uint32_t val; + uint32_t val, mask; + + mask = DC_STATE_DEBUG_MASK_MEMORY_UP | + DC_STATE_DEBUG_MASK_CORES; /* The below bit doesn't need to be cleared ever afterwards */ val = I915_READ(DC_STATE_DEBUG); - if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) { - val |= DC_STATE_DEBUG_MASK_MEMORY_UP; + if ((val & mask) != mask) { + val |= mask; I915_WRITE(DC_STATE_DEBUG, val); POSTING_READ(DC_STATE_DEBUG); } @@ -525,7 +527,7 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state) state = DC_STATE_EN_UPTO_DC5; if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK) - gen9_set_dc_state_debugmask_memory_up(dev_priv); + gen9_set_dc_state_debugmask(dev_priv); val = I915_READ(DC_STATE_EN); DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
Cores need to be included into the debug mask. We don't exactly know what it does but the spec says it must be enabled. So obey. Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_runtime_pm.c | 14 ++++++++------ 2 files changed, 9 insertions(+), 6 deletions(-)