| Message ID | 1455890711-25323-1-git-send-email-michel.thierry@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Feb 19, 2016 at 02:05:11PM +0000, Michel Thierry wrote: > The cache line offset for the Indirect CS context (0x21C8) varies from gen > to gen. > > Cc: Arun Siluvery <arun.siluvery@linux.intel.com> > Signed-off-by: Michel Thierry <michel.thierry@intel.com> > --- > drivers/gpu/drm/i915/intel_lrc.c | 21 +++++++++++++++++++-- > 1 file changed, 19 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 5c0bf02..e707937 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -226,7 +226,8 @@ enum { > FAULT_AND_CONTINUE /* Unsupported */ > }; > #define GEN8_CTX_ID_SHIFT 32 > -#define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 > +#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 > +#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 > > static int intel_lr_context_pin(struct drm_i915_gem_request *rq); > static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring, > @@ -2330,13 +2331,29 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o > if (ring->wa_ctx.obj) { > struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx; > uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj); > + uint32_t indirect_ctx_offset; > > reg_state[CTX_RCS_INDIRECT_CTX+1] = > (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) | > (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); > > + switch (INTEL_INFO(ring->dev)->gen) { > + default: > + DRM_ERROR("Unknown indirect ctx offset for GEN%d\n", > + INTEL_INFO(ring->dev)->gen); > + /* fall through */ MISSING_CASE() -Chris
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 5c0bf02..e707937 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -226,7 +226,8 @@ enum { FAULT_AND_CONTINUE /* Unsupported */ }; #define GEN8_CTX_ID_SHIFT 32 -#define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 +#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 +#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 static int intel_lr_context_pin(struct drm_i915_gem_request *rq); static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring, @@ -2330,13 +2331,29 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o if (ring->wa_ctx.obj) { struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx; uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj); + uint32_t indirect_ctx_offset; reg_state[CTX_RCS_INDIRECT_CTX+1] = (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) | (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); + switch (INTEL_INFO(ring->dev)->gen) { + default: + DRM_ERROR("Unknown indirect ctx offset for GEN%d\n", + INTEL_INFO(ring->dev)->gen); + /* fall through */ + case 9: + indirect_ctx_offset = + GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; + break; + case 8: + indirect_ctx_offset = + GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; + break; + } + reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = - CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6; + indirect_ctx_offset << 6; reg_state[CTX_BB_PER_CTX_PTR+1] = (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
The cache line offset for the Indirect CS context (0x21C8) varies from gen to gen. Cc: Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by: Michel Thierry <michel.thierry@intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-)