@@ -1608,6 +1608,7 @@ void intel_init_pm(struct drm_device *dev);
void intel_pm_setup(struct drm_device *dev);
void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
void intel_gpu_ips_teardown(void);
+void gen6_init_rps_frequencies(struct drm_device *dev);
void intel_init_gt_powersave(struct drm_device *dev);
void intel_cleanup_gt_powersave(struct drm_device *dev);
void intel_enable_gt_powersave(struct drm_device *dev);
@@ -4712,7 +4712,7 @@ int intel_enable_rc6(const struct drm_device *dev)
return i915.enable_rc6;
}
-static void gen6_init_rps_frequencies(struct drm_device *dev)
+void gen6_init_rps_frequencies(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t rp_state_cap;
@@ -92,6 +92,11 @@ void intel_slpc_init(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_i915_gem_object *obj;
+ /* Initialize the rps frequecny values */
+ mutex_lock(&dev_priv->rps.hw_lock);
+ gen6_init_rps_frequencies(dev);
+ mutex_unlock(&dev_priv->rps.hw_lock);
+
/* Allocate shared data structure */
obj = dev_priv->guc.slpc.shared_data_obj;
if (!obj) {