@@ -1135,6 +1135,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
flush_delayed_work(&dev_priv->rps.delayed_resume_work);
+ if (intel_slpc_active(dev))
+ dev_priv->rps.cur_freq = (I915_READ(GEN6_RPNSWREQ) >> 23);
+
if (IS_GEN5(dev)) {
u16 rgvswctl = I915_READ16(MEMSWCTL);
u16 rgvstat = I915_READ16(MEMSTAT_ILK);
@@ -2351,6 +2354,9 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_file *file;
+ if (intel_slpc_active(dev))
+ dev_priv->rps.cur_freq = (I915_READ(GEN6_RPNSWREQ) >> 23);
+
seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
@@ -318,6 +318,8 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
intel_runtime_pm_get(dev_priv);
mutex_lock(&dev_priv->rps.hw_lock);
+ if (intel_slpc_active(dev))
+ dev_priv->rps.cur_freq = (I915_READ(GEN6_RPNSWREQ) >> 23);
ret = intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq);
mutex_unlock(&dev_priv->rps.hw_lock);