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drm/i915/gen9: add WaClearFlowControlGpgpuContextSave

Message ID 1457530558-7137-1-git-send-email-tim.gore@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

tim.gore@intel.com March 9, 2016, 1:35 p.m. UTC 
From: Tim Gore <tim.gore@intel.com>

This allows writes to EU flow control registers. Together
with SIP code from the user-mode driver this resolves a
hang seen in some pre-emption scenarios. Note that this
patch is just the kernel mode part of this workaround.

Signed-off-by: Tim Gore <tim.gore@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

kernel test robot March 9, 2016, 1:54 p.m. UTC | #1 
Hi Tim,

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.5-rc7 next-20160309]
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]

url:    https://github.com/0day-ci/linux/commits/tim-gore-intel-com/drm-i915-gen9-add-WaClearFlowControlGpgpuContextSave/20160309-213806
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x000-201610 (attached as .config)
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All error/warnings (new ones prefixed by >>):

   drivers/gpu/drm/i915/intel_ringbuffer.c: In function 'gen9_init_workarounds':
>> drivers/gpu/drm/i915/intel_ringbuffer.c:926:6: error: 'FLOW_CONTROL_ENABLE' undeclared (first use in this function)
         FLOW_CONTROL_ENABLE |
         ^
   drivers/gpu/drm/i915/intel_ringbuffer.c:773:43: note: in definition of macro 'WA_REG'
      const int r = wa_add(dev_priv, (addr), (mask), (val)); \
                                              ^
>> drivers/gpu/drm/i915/intel_ringbuffer.c:925:2: note: in expansion of macro 'WA_SET_BIT_MASKED'
     WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
     ^
   drivers/gpu/drm/i915/intel_ringbuffer.c:926:6: note: each undeclared identifier is reported only once for each function it appears in
         FLOW_CONTROL_ENABLE |
         ^
   drivers/gpu/drm/i915/intel_ringbuffer.c:773:43: note: in definition of macro 'WA_REG'
      const int r = wa_add(dev_priv, (addr), (mask), (val)); \
                                              ^
>> drivers/gpu/drm/i915/intel_ringbuffer.c:925:2: note: in expansion of macro 'WA_SET_BIT_MASKED'
     WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
     ^

vim +/FLOW_CONTROL_ENABLE +926 drivers/gpu/drm/i915/intel_ringbuffer.c

   919		/* WaDisableKillLogic:bxt,skl */
   920		I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
   921			   ECOCHK_DIS_TLB);
   922	
   923		/* WaClearFlowControlGpgpuContextSave:skl,bxt */
   924		/* WaDisablePartialInstShootdown:skl,bxt */
 > 925		WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 > 926				  FLOW_CONTROL_ENABLE |
   927				  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
   928	
   929		/* Syncing dependencies between camera and graphics:skl,bxt */

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 45ce45a..83ab25a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -920,8 +920,10 @@  static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 		   ECOCHK_DIS_TLB);
 
+	/* WaClearFlowControlGpgpuContextSave:skl,bxt */
 	/* WaDisablePartialInstShootdown:skl,bxt */
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
+			  FLOW_CONTROL_ENABLE |
 			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 
 	/* Syncing dependencies between camera and graphics:skl,bxt */