Message ID | 1457541968-2004-1-git-send-email-tim.gore@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On 09/03/2016 16:46, tim.gore@intel.com wrote: > From: Tim Gore <tim.gore@intel.com> > > This is to fix a GPU hang seen with mid thread pre-emption > and pooled EUs. > > Signed-off-by: Tim Gore <tim.gore@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++++++ > drivers/gpu/drm/i915/intel_lrc.c | 19 +++++++++++++++++++ > 2 files changed, 31 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 7dfc400..0600bc7 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1777,6 +1777,18 @@ enum skl_disp_power_wells { > #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) > #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2)) > > +/* WaClearTdlStateAckDirtyBits */ > +#define GEN8_STATE_ACK 0x20F0 > +#define GEN9_STATE_ACK_SLICE1 0x20F8 > +#define GEN9_STATE_ACK_SLICE2 0x2100 > +#define GEN9_STATE_ACK_TDL0 (1 << 12) > +#define GEN9_STATE_ACK_TDL1 (1 << 13) > +#define GEN9_STATE_ACK_TDL2 (1 << 14) > +#define GEN9_STATE_ACK_TDL3 (1 << 15) > +#define GEN9_SUBSLICE_TDL_ACK_BITS \ > + (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \ > + GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0) > + > #define GFX_MODE _MMIO(0x2520) > #define GFX_MODE_GEN7 _MMIO(0x229c) > #define RING_MODE_GEN7(ring) _MMIO((ring)->mmio_base+0x29c) > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 6fcbf6b..c36398d 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1447,6 +1447,25 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring, > wa_ctx_emit(batch, index, MI_NOOP); > } > > + /* WaClearTdlStateAckDirtyBits:bxt */ > + if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_B0)) { this should be, IS_BXT_REVID(dev, 0, BXT_REVID_B0) regards Arun > + wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4)); > + > + wa_ctx_emit(batch, index, GEN8_STATE_ACK); > + wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); > + > + wa_ctx_emit(batch, index, GEN9_STATE_ACK_SLICE1); > + wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); > + > + wa_ctx_emit(batch, index, GEN9_STATE_ACK_SLICE2); > + wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); > + > + wa_ctx_emit(batch, index, GEN7_ROW_CHICKEN2); > + /* dummy write to CS, mask bits are 0 to ensure the register is not modified */ > + wa_ctx_emit(batch, index, 0x0); > + wa_ctx_emit(batch, index, MI_NOOP); > + } > + > /* WaDisableCtxRestoreArbitration:skl,bxt */ > if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || > IS_BXT_REVID(dev, 0, BXT_REVID_A1)) >
Hi Tim, [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on v4.5-rc7 next-20160309] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url: https://github.com/0day-ci/linux/commits/tim-gore-intel-com/drm-i915-implement-WaClearTdlStateAckDirtyBits/20160310-004816 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: i386-randconfig-x000-201610 (attached as .config) reproduce: # save the attached .config to linux build tree make ARCH=i386 All error/warnings (new ones prefixed by >>): drivers/gpu/drm/i915/intel_lrc.c: In function 'gen9_init_perctx_bb': >> drivers/gpu/drm/i915/intel_lrc.c:1216:18: error: incompatible types when assigning to type 'uint32_t {aka unsigned int}' from type 'i915_reg_t {aka const struct <anonymous>}' batch[__index] = (cmd); \ ^ >> drivers/gpu/drm/i915/intel_lrc.c:1463:3: note: in expansion of macro 'wa_ctx_emit' wa_ctx_emit(batch, index, GEN7_ROW_CHICKEN2); ^ vim +1216 drivers/gpu/drm/i915/intel_lrc.c 83b8a982 Arun Siluvery 2015-07-08 1210 #define wa_ctx_emit(batch, index, cmd) \ 17ee950d Arun Siluvery 2015-06-19 1211 do { \ 83b8a982 Arun Siluvery 2015-07-08 1212 int __index = (index)++; \ 83b8a982 Arun Siluvery 2015-07-08 1213 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \ 17ee950d Arun Siluvery 2015-06-19 1214 return -ENOSPC; \ 17ee950d Arun Siluvery 2015-06-19 1215 } \ 83b8a982 Arun Siluvery 2015-07-08 @1216 batch[__index] = (cmd); \ 17ee950d Arun Siluvery 2015-06-19 1217 } while (0) 17ee950d Arun Siluvery 2015-06-19 1218 8f40db77 Ville Syrjälä 2015-11-04 1219 #define wa_ctx_emit_reg(batch, index, reg) \ :::::: The code at line 1216 was first introduced by commit :::::: 83b8a982b101c48fc025066a7b08beaf6fa756f0 drm/i915: Update wa_ctx_emit() macro as per kernel coding guidelines :::::: TO: Arun Siluvery <arun.siluvery@linux.intel.com> :::::: CC: Daniel Vetter <daniel.vetter@ffwll.ch> --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
On 09/03/2016 16:46, tim.gore@intel.com wrote: > From: Tim Gore <tim.gore@intel.com> > > This is to fix a GPU hang seen with mid thread pre-emption > and pooled EUs. > > Signed-off-by: Tim Gore <tim.gore@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++++++ > drivers/gpu/drm/i915/intel_lrc.c | 19 +++++++++++++++++++ > 2 files changed, 31 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 7dfc400..0600bc7 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1777,6 +1777,18 @@ enum skl_disp_power_wells { > #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) > #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2)) > > +/* WaClearTdlStateAckDirtyBits */ > +#define GEN8_STATE_ACK 0x20F0 > +#define GEN9_STATE_ACK_SLICE1 0x20F8 > +#define GEN9_STATE_ACK_SLICE2 0x2100 _MMIO(reg_addr) regards Arun > +#define GEN9_STATE_ACK_TDL0 (1 << 12) > +#define GEN9_STATE_ACK_TDL1 (1 << 13) > +#define GEN9_STATE_ACK_TDL2 (1 << 14) > +#define GEN9_STATE_ACK_TDL3 (1 << 15) > +#define GEN9_SUBSLICE_TDL_ACK_BITS \ > + (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \ > + GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0) > + > #define GFX_MODE _MMIO(0x2520) > #define GFX_MODE_GEN7 _MMIO(0x229c) > #define RING_MODE_GEN7(ring) _MMIO((ring)->mmio_base+0x29c) > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 6fcbf6b..c36398d 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1447,6 +1447,25 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring, > wa_ctx_emit(batch, index, MI_NOOP); > } > > + /* WaClearTdlStateAckDirtyBits:bxt */ > + if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_B0)) { > + wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4)); > + > + wa_ctx_emit(batch, index, GEN8_STATE_ACK); > + wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); > + > + wa_ctx_emit(batch, index, GEN9_STATE_ACK_SLICE1); > + wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); > + > + wa_ctx_emit(batch, index, GEN9_STATE_ACK_SLICE2); > + wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); > + > + wa_ctx_emit(batch, index, GEN7_ROW_CHICKEN2); > + /* dummy write to CS, mask bits are 0 to ensure the register is not modified */ > + wa_ctx_emit(batch, index, 0x0); > + wa_ctx_emit(batch, index, MI_NOOP); > + } > + > /* WaDisableCtxRestoreArbitration:skl,bxt */ > if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || > IS_BXT_REVID(dev, 0, BXT_REVID_A1)) >
Hi Tim,
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.5-rc7 next-20160309]
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]
url: https://github.com/0day-ci/linux/commits/tim-gore-intel-com/drm-i915-implement-WaClearTdlStateAckDirtyBits/20160310-004816
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-rhel (attached as .config)
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/intel_lrc.c: In function 'gen9_init_perctx_bb':
>> drivers/gpu/drm/i915/intel_lrc.c:1216:18: error: incompatible types when assigning to type 'uint32_t' from type 'i915_reg_t'
batch[__index] = (cmd); \
^
drivers/gpu/drm/i915/intel_lrc.c:1463:3: note: in expansion of macro 'wa_ctx_emit'
wa_ctx_emit(batch, index, GEN7_ROW_CHICKEN2);
^
vim +1216 drivers/gpu/drm/i915/intel_lrc.c
83b8a982 Arun Siluvery 2015-07-08 1210 #define wa_ctx_emit(batch, index, cmd) \
17ee950d Arun Siluvery 2015-06-19 1211 do { \
83b8a982 Arun Siluvery 2015-07-08 1212 int __index = (index)++; \
83b8a982 Arun Siluvery 2015-07-08 1213 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
17ee950d Arun Siluvery 2015-06-19 1214 return -ENOSPC; \
17ee950d Arun Siluvery 2015-06-19 1215 } \
83b8a982 Arun Siluvery 2015-07-08 @1216 batch[__index] = (cmd); \
17ee950d Arun Siluvery 2015-06-19 1217 } while (0)
17ee950d Arun Siluvery 2015-06-19 1218
8f40db77 Ville Syrjälä 2015-11-04 1219 #define wa_ctx_emit_reg(batch, index, reg) \
:::::: The code at line 1216 was first introduced by commit
:::::: 83b8a982b101c48fc025066a7b08beaf6fa756f0 drm/i915: Update wa_ctx_emit() macro as per kernel coding guidelines
:::::: TO: Arun Siluvery <arun.siluvery@linux.intel.com>
:::::: CC: Daniel Vetter <daniel.vetter@ffwll.ch>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7dfc400..0600bc7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1777,6 +1777,18 @@ enum skl_disp_power_wells { #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2)) +/* WaClearTdlStateAckDirtyBits */ +#define GEN8_STATE_ACK 0x20F0 +#define GEN9_STATE_ACK_SLICE1 0x20F8 +#define GEN9_STATE_ACK_SLICE2 0x2100 +#define GEN9_STATE_ACK_TDL0 (1 << 12) +#define GEN9_STATE_ACK_TDL1 (1 << 13) +#define GEN9_STATE_ACK_TDL2 (1 << 14) +#define GEN9_STATE_ACK_TDL3 (1 << 15) +#define GEN9_SUBSLICE_TDL_ACK_BITS \ + (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \ + GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0) + #define GFX_MODE _MMIO(0x2520) #define GFX_MODE_GEN7 _MMIO(0x229c) #define RING_MODE_GEN7(ring) _MMIO((ring)->mmio_base+0x29c) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 6fcbf6b..c36398d 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1447,6 +1447,25 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring, wa_ctx_emit(batch, index, MI_NOOP); } + /* WaClearTdlStateAckDirtyBits:bxt */ + if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_B0)) { + wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4)); + + wa_ctx_emit(batch, index, GEN8_STATE_ACK); + wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); + + wa_ctx_emit(batch, index, GEN9_STATE_ACK_SLICE1); + wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); + + wa_ctx_emit(batch, index, GEN9_STATE_ACK_SLICE2); + wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); + + wa_ctx_emit(batch, index, GEN7_ROW_CHICKEN2); + /* dummy write to CS, mask bits are 0 to ensure the register is not modified */ + wa_ctx_emit(batch, index, 0x0); + wa_ctx_emit(batch, index, MI_NOOP); + } + /* WaDisableCtxRestoreArbitration:skl,bxt */ if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || IS_BXT_REVID(dev, 0, BXT_REVID_A1))