From patchwork Thu Mar 10 11:03:34 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Derek Morton X-Patchwork-Id: 8555621 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E5669C0553 for ; Thu, 10 Mar 2016 11:05:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CF9B02034E for ; Thu, 10 Mar 2016 11:05:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id CF0612034C for ; Thu, 10 Mar 2016 11:05:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EE1056E93C; Thu, 10 Mar 2016 11:04:59 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 9CEB06E220 for ; Thu, 10 Mar 2016 11:04:18 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP; 10 Mar 2016 03:04:20 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,315,1455004800"; d="scan'208";a="906892115" Received: from djmorton-linux2.isw.intel.com ([10.102.226.90]) by orsmga001.jf.intel.com with ESMTP; 10 Mar 2016 03:04:17 -0800 From: Derek Morton To: intel-gfx@lists.freedesktop.org Date: Thu, 10 Mar 2016 11:03:34 +0000 Message-Id: <1457607814-18751-7-git-send-email-derek.j.morton@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1457607814-18751-1-git-send-email-derek.j.morton@intel.com> References: <1457607814-18751-1-git-send-email-derek.j.morton@intel.com> Cc: daniel.vetter@ffwll.com Subject: [Intel-gfx] [PATCH i-g-t v3 6/6] gem_scheduler: Added subtests to test priority bumping X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When a higher priority batch buffer bumps a lower priority batch buffer all batch buffers in the scheduler queue get a small priority increase. Added a subtest to check this behaviour. Requested by Joonas Lahtinen during scheduler code review Signed-off-by: Derek Morton --- tests/gem_scheduler.c | 134 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/tests/gem_scheduler.c b/tests/gem_scheduler.c index 126ee97..0fbc6e9 100644 --- a/tests/gem_scheduler.c +++ b/tests/gem_scheduler.c @@ -254,6 +254,134 @@ static void run_test_basic(int in_flight, int ringid, int priority) free(in_flight_bbs); } + +/* Test priority bump behaviour. + * When a batch buffer is bumped by a higher priority batch buffer all other + * batch buffers in the scheduler queue get their priority increased slightly. + * Submit two delay batch buffers then fill the in flight queue. Submit a + * slightly reduced priority batch buffer and a normal priority batch buffer. + * When the first delay batch buffer completes priority bumping should occur. + * Submit another normal priority batch buffer. It should not overtake the + * reduced priority batch buffer as its priority has been bumped. + */ +#define NBR_PRIO_BUMP_FDs (4) +static void run_test_priority_bump(int in_flight, int ringid) +{ + int fd[NBR_PRIO_BUMP_FDs]; + int loop; + drm_intel_bufmgr *bufmgr[NBR_PRIO_BUMP_FDs]; + uint32_t *delay_buf, *delay2_buf, *ts1_buf, *ts2_buf, *ts3_buf; + struct intel_batchbuffer *ts1_bb, *ts2_bb, *ts3_bb; + struct intel_batchbuffer **in_flight_bbs; + uint32_t calibrated_1s; + drm_intel_bo *delay_bo, *delay2_bo ,*ts1_bo, *ts2_bo, *ts3_bo; + + in_flight_bbs = malloc(in_flight * sizeof(struct intel_batchbuffer *)); + igt_assert(in_flight_bbs); + + /* Need multiple i915 fd's. Scheduler will not change execution order of + * batch buffers from the same context. + */ + for(loop=0; loop < NBR_PRIO_BUMP_FDs; loop++) + init_context(&(fd[loop]), &(bufmgr[loop]), ringid); + + /* Lower priority of first timestamp batch buffer + * Second timestamp batch buffer should overtake the first + * Second should then get bumped so the third does not overtake it + */ + set_priority(fd[1], -1); + + /* Create buffer objects */ + delay_bo = create_and_check_bo(bufmgr[0], "delay bo"); + delay2_bo = create_and_check_bo(bufmgr[0], "delay bo2"); + ts1_bo = create_and_check_bo(bufmgr[1], "ts1 bo"); + ts2_bo = create_and_check_bo(bufmgr[2], "ts2 bo"); + ts3_bo = create_and_check_bo(bufmgr[3], "ts23 bo"); + + /* Put some non zero values in the delay bo */ + { + uint32_t data=0xffffffff; + drm_intel_bo_subdata(delay_bo, 0, 4, &data); + drm_intel_bo_subdata(delay2_bo, 0, 4, &data); + } + + calibrated_1s = igt_calibrate_delay_bb(fd[0], bufmgr[0], ringid); + + /* Batch buffers to fill the in flight queue */ + in_flight_bbs[0] = create_delay_bb(fd[0], bufmgr[0], ringid, calibrated_1s, delay_bo); + in_flight_bbs[1] = create_delay_bb(fd[0], bufmgr[0], ringid, calibrated_1s, delay2_bo); + for(loop = 2; loop < in_flight; loop++) + in_flight_bbs[loop] = create_noop_bb(fd[0], bufmgr[0], 5); + + /* Extra batch buffers in the scheduler queue */ + ts1_bb = create_timestamp_bb(fd[1], bufmgr[1], ringid, ts1_bo, NULL, false); + ts2_bb = create_timestamp_bb(fd[2], bufmgr[2], ringid, ts2_bo, NULL, false); + ts3_bb = create_timestamp_bb(fd[3], bufmgr[3], ringid, ts3_bo, NULL, false); + + /* Flush batchbuffers */ + for(loop = 0; loop < in_flight; loop++) + intel_batchbuffer_flush_on_ring(in_flight_bbs[loop], ringid); + intel_batchbuffer_flush_on_ring(ts1_bb, ringid); + intel_batchbuffer_flush_on_ring(ts2_bb, ringid); + + /* This will not return until the bo has finished executing */ + drm_intel_bo_map(delay_bo, 0); + /* Once the first delay is complete and any bumping has occured, submit + * the final batch buffer + */ + intel_batchbuffer_flush_on_ring(ts3_bb, ringid); + + drm_intel_bo_map(delay2_bo, 0); + drm_intel_bo_map(ts1_bo, 0); + drm_intel_bo_map(ts2_bo, 0); + drm_intel_bo_map(ts3_bo, 0); + + delay_buf = delay_bo->virtual; + delay2_buf = delay2_bo->virtual; + ts1_buf = ts1_bo->virtual; + ts2_buf = ts2_bo->virtual; + ts3_buf = ts3_bo->virtual; + + igt_debug("Delay Timestamp = 0x%08" PRIx32 "\n", delay_buf[2]); + igt_debug("Delay Timestamp = 0x%08" PRIx32 "\n", delay2_buf[2]); + igt_debug("TS1 Timestamp = 0x%08" PRIx32 "\n", ts1_buf[0]); + igt_debug("TS2 Timestamp = 0x%08" PRIx32 "\n", ts2_buf[0]); + igt_debug("TS3 Timestamp = 0x%08" PRIx32 "\n", ts3_buf[0]); + + /* buf[0] in the target buffer should be 0 if the batch buffer completed */ + igt_assert_f(delay_buf[0] == 0, + "delay_buf[0] expected 0x0, got 0x%" PRIx32 "\n", delay_buf[0]); + + igt_assert_f(igt_compare_timestamps(delay_buf[2], ts1_buf[0]), + "Delay ts (0x%08" PRIx32 ") > TS1 ts (0x%08" PRIx32 ")\n", + delay_buf[2], ts1_buf[0]); + + igt_assert_f(igt_compare_timestamps(ts2_buf[0], ts1_buf[0]), + "TS2 ts (0x%08" PRIx32 ") > TS1 ts (0x%08" PRIx32 ")\n", + ts2_buf[0], ts1_buf[0]); + + igt_assert_f(igt_compare_timestamps(ts1_buf[0], ts3_buf[0]), + "TS1 ts (0x%08" PRIx32 ") > TS3 ts (0x%08" PRIx32 ")\n", + ts1_buf[0], ts3_buf[0]); + + /* Cleanup */ + for(loop = 0; loop < in_flight; loop++) + intel_batchbuffer_free(in_flight_bbs[loop]); + intel_batchbuffer_free(ts1_bb); + intel_batchbuffer_free(ts2_bb); + + drm_intel_bo_unreference(delay_bo); + drm_intel_bo_unreference(delay2_bo); + drm_intel_bo_unreference(ts1_bo); + drm_intel_bo_unreference(ts2_bo); + drm_intel_bo_unreference(ts3_bo); + for(loop = 0; loop < NBR_PRIO_BUMP_FDs; loop++) { + drm_intel_bufmgr_destroy(bufmgr[loop]); + close(fd[loop]); + } + free(in_flight_bbs); +} + /* Dependency test. * write=0, Submit batch buffers with read dependencies to all rings. Delay one * with a long executing batch buffer. Check the others are not held up. @@ -490,6 +618,12 @@ igt_main run_test_dependency(in_flight, loop, true); } + for (loop=0; loop < NBR_RINGS; loop++) + igt_subtest_f("%s-priority-bump", rings[loop].name) { + gem_require_ring(fd, rings[loop].id); + run_test_priority_bump(in_flight, rings[loop].id); + } + igt_fixture { close(fd); }