| Message ID | 1459515767-29228-10-git-send-email-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Apr 01, 2016 at 04:02:40PM +0300, Imre Deak wrote: > For internal APIs passing dev_priv is preferred to reduce indirections, > so convert over a few DDI PHY, CDCLK helpers. > > No functional change. > > Signed-off-by: Imre Deak <imre.deak@intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_drv.c | 12 ++++-------- > drivers/gpu/drm/i915/intel_ddi.c | 10 ++++------ > drivers/gpu/drm/i915/intel_display.c | 18 +++++++----------- > drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 ++-- > drivers/gpu/drm/i915/intel_drv.h | 8 ++++---- > 5 files changed, 21 insertions(+), 31 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index aa7df10..3998f6a 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -1070,12 +1070,10 @@ static int hsw_suspend_complete(struct drm_i915_private *dev_priv) > > static int bxt_suspend_complete(struct drm_i915_private *dev_priv) > { > - struct drm_device *dev = dev_priv->dev; > - > /* TODO: when DC5 support is added disable DC5 here. */ > > - broxton_ddi_phy_uninit(dev); > - broxton_uninit_cdclk(dev); > + broxton_ddi_phy_uninit(dev_priv); > + broxton_uninit_cdclk(dev_priv); > bxt_enable_dc9(dev_priv); > > return 0; > @@ -1083,8 +1081,6 @@ static int bxt_suspend_complete(struct drm_i915_private *dev_priv) > > static int bxt_resume_prepare(struct drm_i915_private *dev_priv) > { > - struct drm_device *dev = dev_priv->dev; > - > /* TODO: when CSR FW support is added make sure the FW is loaded */ > > bxt_disable_dc9(dev_priv); > @@ -1093,8 +1089,8 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv) > * TODO: when DC5 support is added enable DC5 here if the CSR FW > * is available. > */ > - broxton_init_cdclk(dev); > - broxton_ddi_phy_init(dev); > + broxton_init_cdclk(dev_priv); > + broxton_ddi_phy_init(dev_priv); > > return 0; > } > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index f91306e..29017a4 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1834,11 +1834,11 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv, > I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); > } > > -void broxton_ddi_phy_init(struct drm_device *dev) > +void broxton_ddi_phy_init(struct drm_i915_private *dev_priv) > { > /* Enable PHY1 first since it provides Rcomp for PHY0 */ > - broxton_phy_init(dev->dev_private, DPIO_PHY1); > - broxton_phy_init(dev->dev_private, DPIO_PHY0); > + broxton_phy_init(dev_priv, DPIO_PHY1); > + broxton_phy_init(dev_priv, DPIO_PHY0); > } > > static void broxton_phy_uninit(struct drm_i915_private *dev_priv, > @@ -1851,10 +1851,8 @@ static void broxton_phy_uninit(struct drm_i915_private *dev_priv, > I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); > } > > -void broxton_ddi_phy_uninit(struct drm_device *dev) > +void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv) > { > - struct drm_i915_private *dev_priv = dev->dev_private; > - > broxton_phy_uninit(dev_priv, DPIO_PHY1); > broxton_phy_uninit(dev_priv, DPIO_PHY0); > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index e6b5ee5..d9da89d 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5322,9 +5322,8 @@ static void intel_update_cdclk(struct drm_device *dev) > intel_update_max_cdclk(dev); > } > > -static void broxton_set_cdclk(struct drm_device *dev, int frequency) > +static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency) > { > - struct drm_i915_private *dev_priv = dev->dev_private; > uint32_t divider; > uint32_t ratio; > uint32_t current_freq; > @@ -5438,12 +5437,11 @@ static void broxton_set_cdclk(struct drm_device *dev, int frequency) > return; > } > > - intel_update_cdclk(dev); > + intel_update_cdclk(dev_priv->dev); > } > > -void broxton_init_cdclk(struct drm_device *dev) > +void broxton_init_cdclk(struct drm_i915_private *dev_priv) > { > - struct drm_i915_private *dev_priv = dev->dev_private; > uint32_t val; > > /* > @@ -5472,7 +5470,7 @@ void broxton_init_cdclk(struct drm_device *dev) > * - check if setting the max (or any) cdclk freq is really necessary > * here, it belongs to modeset time > */ > - broxton_set_cdclk(dev, 624000); > + broxton_set_cdclk(dev_priv, 624000); > > I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); > POSTING_READ(DBUF_CTL); > @@ -5483,10 +5481,8 @@ void broxton_init_cdclk(struct drm_device *dev) > DRM_ERROR("DBuf power enable timeout!\n"); > } > > -void broxton_uninit_cdclk(struct drm_device *dev) > +void broxton_uninit_cdclk(struct drm_i915_private *dev_priv) > { > - struct drm_i915_private *dev_priv = dev->dev_private; > - > I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); > POSTING_READ(DBUF_CTL); > > @@ -5496,7 +5492,7 @@ void broxton_uninit_cdclk(struct drm_device *dev) > DRM_ERROR("DBuf power disable timeout!\n"); > > /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ > - broxton_set_cdclk(dev, 19200); > + broxton_set_cdclk(dev_priv, 19200); > > intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); > } > @@ -9532,7 +9528,7 @@ static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) > to_intel_atomic_state(old_state); > unsigned int req_cdclk = old_intel_state->dev_cdclk; > > - broxton_set_cdclk(dev, req_cdclk); > + broxton_set_cdclk(to_i915(dev), req_cdclk); > } > > /* compute the max rate for new configuration */ > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c > index 1175eeb..fbe88b8 100644 > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c > @@ -1645,8 +1645,8 @@ static void intel_ddi_pll_init(struct drm_device *dev) > if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) > DRM_ERROR("LCPLL1 is disabled\n"); > } else if (IS_BROXTON(dev)) { > - broxton_init_cdclk(dev); > - broxton_ddi_phy_init(dev); > + broxton_init_cdclk(dev_priv); > + broxton_ddi_phy_init(dev_priv); > } else { > /* > * The LCPLL register should be turned on by the BIOS. For now > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 8ba2ac3..e8843a7 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -1222,10 +1222,10 @@ void intel_prepare_reset(struct drm_device *dev); > void intel_finish_reset(struct drm_device *dev); > void hsw_enable_pc8(struct drm_i915_private *dev_priv); > void hsw_disable_pc8(struct drm_i915_private *dev_priv); > -void broxton_init_cdclk(struct drm_device *dev); > -void broxton_uninit_cdclk(struct drm_device *dev); > -void broxton_ddi_phy_init(struct drm_device *dev); > -void broxton_ddi_phy_uninit(struct drm_device *dev); > +void broxton_init_cdclk(struct drm_i915_private *dev_priv); > +void broxton_uninit_cdclk(struct drm_i915_private *dev_priv); > +void broxton_ddi_phy_init(struct drm_i915_private *dev_priv); > +void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv); > void bxt_enable_dc9(struct drm_i915_private *dev_priv); > void bxt_disable_dc9(struct drm_i915_private *dev_priv); > void skl_init_cdclk(struct drm_i915_private *dev_priv); > -- > 2.5.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Fri, Apr 01, 2016 at 04:02:40PM +0300, Imre Deak wrote: > For internal APIs passing dev_priv is preferred to reduce indirections, > so convert over a few DDI PHY, CDCLK helpers. > > No functional change. > > Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: David Weinehall <david.weinehall@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.c | 12 ++++-------- > drivers/gpu/drm/i915/intel_ddi.c | 10 ++++------ > drivers/gpu/drm/i915/intel_display.c | 18 +++++++----------- > drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 ++-- > drivers/gpu/drm/i915/intel_drv.h | 8 ++++---- > 5 files changed, 21 insertions(+), 31 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index aa7df10..3998f6a 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -1070,12 +1070,10 @@ static int hsw_suspend_complete(struct drm_i915_private *dev_priv) > > static int bxt_suspend_complete(struct drm_i915_private *dev_priv) > { > - struct drm_device *dev = dev_priv->dev; > - > /* TODO: when DC5 support is added disable DC5 here. */ > > - broxton_ddi_phy_uninit(dev); > - broxton_uninit_cdclk(dev); > + broxton_ddi_phy_uninit(dev_priv); > + broxton_uninit_cdclk(dev_priv); > bxt_enable_dc9(dev_priv); > > return 0; > @@ -1083,8 +1081,6 @@ static int bxt_suspend_complete(struct drm_i915_private *dev_priv) > > static int bxt_resume_prepare(struct drm_i915_private *dev_priv) > { > - struct drm_device *dev = dev_priv->dev; > - > /* TODO: when CSR FW support is added make sure the FW is loaded */ > > bxt_disable_dc9(dev_priv); > @@ -1093,8 +1089,8 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv) > * TODO: when DC5 support is added enable DC5 here if the CSR FW > * is available. > */ > - broxton_init_cdclk(dev); > - broxton_ddi_phy_init(dev); > + broxton_init_cdclk(dev_priv); > + broxton_ddi_phy_init(dev_priv); > > return 0; > } > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index f91306e..29017a4 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1834,11 +1834,11 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv, > I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); > } > > -void broxton_ddi_phy_init(struct drm_device *dev) > +void broxton_ddi_phy_init(struct drm_i915_private *dev_priv) > { > /* Enable PHY1 first since it provides Rcomp for PHY0 */ > - broxton_phy_init(dev->dev_private, DPIO_PHY1); > - broxton_phy_init(dev->dev_private, DPIO_PHY0); > + broxton_phy_init(dev_priv, DPIO_PHY1); > + broxton_phy_init(dev_priv, DPIO_PHY0); > } > > static void broxton_phy_uninit(struct drm_i915_private *dev_priv, > @@ -1851,10 +1851,8 @@ static void broxton_phy_uninit(struct drm_i915_private *dev_priv, > I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); > } > > -void broxton_ddi_phy_uninit(struct drm_device *dev) > +void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv) > { > - struct drm_i915_private *dev_priv = dev->dev_private; > - > broxton_phy_uninit(dev_priv, DPIO_PHY1); > broxton_phy_uninit(dev_priv, DPIO_PHY0); > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index e6b5ee5..d9da89d 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5322,9 +5322,8 @@ static void intel_update_cdclk(struct drm_device *dev) > intel_update_max_cdclk(dev); > } > > -static void broxton_set_cdclk(struct drm_device *dev, int frequency) > +static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency) > { > - struct drm_i915_private *dev_priv = dev->dev_private; > uint32_t divider; > uint32_t ratio; > uint32_t current_freq; > @@ -5438,12 +5437,11 @@ static void broxton_set_cdclk(struct drm_device *dev, int frequency) > return; > } > > - intel_update_cdclk(dev); > + intel_update_cdclk(dev_priv->dev); > } > > -void broxton_init_cdclk(struct drm_device *dev) > +void broxton_init_cdclk(struct drm_i915_private *dev_priv) > { > - struct drm_i915_private *dev_priv = dev->dev_private; > uint32_t val; > > /* > @@ -5472,7 +5470,7 @@ void broxton_init_cdclk(struct drm_device *dev) > * - check if setting the max (or any) cdclk freq is really necessary > * here, it belongs to modeset time > */ > - broxton_set_cdclk(dev, 624000); > + broxton_set_cdclk(dev_priv, 624000); > > I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); > POSTING_READ(DBUF_CTL); > @@ -5483,10 +5481,8 @@ void broxton_init_cdclk(struct drm_device *dev) > DRM_ERROR("DBuf power enable timeout!\n"); > } > > -void broxton_uninit_cdclk(struct drm_device *dev) > +void broxton_uninit_cdclk(struct drm_i915_private *dev_priv) > { > - struct drm_i915_private *dev_priv = dev->dev_private; > - > I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); > POSTING_READ(DBUF_CTL); > > @@ -5496,7 +5492,7 @@ void broxton_uninit_cdclk(struct drm_device *dev) > DRM_ERROR("DBuf power disable timeout!\n"); > > /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ > - broxton_set_cdclk(dev, 19200); > + broxton_set_cdclk(dev_priv, 19200); > > intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); > } > @@ -9532,7 +9528,7 @@ static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) > to_intel_atomic_state(old_state); > unsigned int req_cdclk = old_intel_state->dev_cdclk; > > - broxton_set_cdclk(dev, req_cdclk); > + broxton_set_cdclk(to_i915(dev), req_cdclk); > } > > /* compute the max rate for new configuration */ > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c > index 1175eeb..fbe88b8 100644 > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c > @@ -1645,8 +1645,8 @@ static void intel_ddi_pll_init(struct drm_device *dev) > if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) > DRM_ERROR("LCPLL1 is disabled\n"); > } else if (IS_BROXTON(dev)) { > - broxton_init_cdclk(dev); > - broxton_ddi_phy_init(dev); > + broxton_init_cdclk(dev_priv); > + broxton_ddi_phy_init(dev_priv); > } else { > /* > * The LCPLL register should be turned on by the BIOS. For now > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 8ba2ac3..e8843a7 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -1222,10 +1222,10 @@ void intel_prepare_reset(struct drm_device *dev); > void intel_finish_reset(struct drm_device *dev); > void hsw_enable_pc8(struct drm_i915_private *dev_priv); > void hsw_disable_pc8(struct drm_i915_private *dev_priv); > -void broxton_init_cdclk(struct drm_device *dev); > -void broxton_uninit_cdclk(struct drm_device *dev); > -void broxton_ddi_phy_init(struct drm_device *dev); > -void broxton_ddi_phy_uninit(struct drm_device *dev); > +void broxton_init_cdclk(struct drm_i915_private *dev_priv); > +void broxton_uninit_cdclk(struct drm_i915_private *dev_priv); > +void broxton_ddi_phy_init(struct drm_i915_private *dev_priv); > +void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv); > void bxt_enable_dc9(struct drm_i915_private *dev_priv); > void bxt_disable_dc9(struct drm_i915_private *dev_priv); > void skl_init_cdclk(struct drm_i915_private *dev_priv); > -- > 2.5.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index aa7df10..3998f6a 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1070,12 +1070,10 @@ static int hsw_suspend_complete(struct drm_i915_private *dev_priv) static int bxt_suspend_complete(struct drm_i915_private *dev_priv) { - struct drm_device *dev = dev_priv->dev; - /* TODO: when DC5 support is added disable DC5 here. */ - broxton_ddi_phy_uninit(dev); - broxton_uninit_cdclk(dev); + broxton_ddi_phy_uninit(dev_priv); + broxton_uninit_cdclk(dev_priv); bxt_enable_dc9(dev_priv); return 0; @@ -1083,8 +1081,6 @@ static int bxt_suspend_complete(struct drm_i915_private *dev_priv) static int bxt_resume_prepare(struct drm_i915_private *dev_priv) { - struct drm_device *dev = dev_priv->dev; - /* TODO: when CSR FW support is added make sure the FW is loaded */ bxt_disable_dc9(dev_priv); @@ -1093,8 +1089,8 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv) * TODO: when DC5 support is added enable DC5 here if the CSR FW * is available. */ - broxton_init_cdclk(dev); - broxton_ddi_phy_init(dev); + broxton_init_cdclk(dev_priv); + broxton_ddi_phy_init(dev_priv); return 0; } diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index f91306e..29017a4 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1834,11 +1834,11 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv, I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); } -void broxton_ddi_phy_init(struct drm_device *dev) +void broxton_ddi_phy_init(struct drm_i915_private *dev_priv) { /* Enable PHY1 first since it provides Rcomp for PHY0 */ - broxton_phy_init(dev->dev_private, DPIO_PHY1); - broxton_phy_init(dev->dev_private, DPIO_PHY0); + broxton_phy_init(dev_priv, DPIO_PHY1); + broxton_phy_init(dev_priv, DPIO_PHY0); } static void broxton_phy_uninit(struct drm_i915_private *dev_priv, @@ -1851,10 +1851,8 @@ static void broxton_phy_uninit(struct drm_i915_private *dev_priv, I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); } -void broxton_ddi_phy_uninit(struct drm_device *dev) +void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = dev->dev_private; - broxton_phy_uninit(dev_priv, DPIO_PHY1); broxton_phy_uninit(dev_priv, DPIO_PHY0); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index e6b5ee5..d9da89d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5322,9 +5322,8 @@ static void intel_update_cdclk(struct drm_device *dev) intel_update_max_cdclk(dev); } -static void broxton_set_cdclk(struct drm_device *dev, int frequency) +static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency) { - struct drm_i915_private *dev_priv = dev->dev_private; uint32_t divider; uint32_t ratio; uint32_t current_freq; @@ -5438,12 +5437,11 @@ static void broxton_set_cdclk(struct drm_device *dev, int frequency) return; } - intel_update_cdclk(dev); + intel_update_cdclk(dev_priv->dev); } -void broxton_init_cdclk(struct drm_device *dev) +void broxton_init_cdclk(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = dev->dev_private; uint32_t val; /* @@ -5472,7 +5470,7 @@ void broxton_init_cdclk(struct drm_device *dev) * - check if setting the max (or any) cdclk freq is really necessary * here, it belongs to modeset time */ - broxton_set_cdclk(dev, 624000); + broxton_set_cdclk(dev_priv, 624000); I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); POSTING_READ(DBUF_CTL); @@ -5483,10 +5481,8 @@ void broxton_init_cdclk(struct drm_device *dev) DRM_ERROR("DBuf power enable timeout!\n"); } -void broxton_uninit_cdclk(struct drm_device *dev) +void broxton_uninit_cdclk(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = dev->dev_private; - I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); POSTING_READ(DBUF_CTL); @@ -5496,7 +5492,7 @@ void broxton_uninit_cdclk(struct drm_device *dev) DRM_ERROR("DBuf power disable timeout!\n"); /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ - broxton_set_cdclk(dev, 19200); + broxton_set_cdclk(dev_priv, 19200); intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); } @@ -9532,7 +9528,7 @@ static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) to_intel_atomic_state(old_state); unsigned int req_cdclk = old_intel_state->dev_cdclk; - broxton_set_cdclk(dev, req_cdclk); + broxton_set_cdclk(to_i915(dev), req_cdclk); } /* compute the max rate for new configuration */ diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 1175eeb..fbe88b8 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -1645,8 +1645,8 @@ static void intel_ddi_pll_init(struct drm_device *dev) if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) DRM_ERROR("LCPLL1 is disabled\n"); } else if (IS_BROXTON(dev)) { - broxton_init_cdclk(dev); - broxton_ddi_phy_init(dev); + broxton_init_cdclk(dev_priv); + broxton_ddi_phy_init(dev_priv); } else { /* * The LCPLL register should be turned on by the BIOS. For now diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 8ba2ac3..e8843a7 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1222,10 +1222,10 @@ void intel_prepare_reset(struct drm_device *dev); void intel_finish_reset(struct drm_device *dev); void hsw_enable_pc8(struct drm_i915_private *dev_priv); void hsw_disable_pc8(struct drm_i915_private *dev_priv); -void broxton_init_cdclk(struct drm_device *dev); -void broxton_uninit_cdclk(struct drm_device *dev); -void broxton_ddi_phy_init(struct drm_device *dev); -void broxton_ddi_phy_uninit(struct drm_device *dev); +void broxton_init_cdclk(struct drm_i915_private *dev_priv); +void broxton_uninit_cdclk(struct drm_i915_private *dev_priv); +void broxton_ddi_phy_init(struct drm_i915_private *dev_priv); +void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv); void bxt_enable_dc9(struct drm_i915_private *dev_priv); void bxt_disable_dc9(struct drm_i915_private *dev_priv); void skl_init_cdclk(struct drm_i915_private *dev_priv);
For internal APIs passing dev_priv is preferred to reduce indirections, so convert over a few DDI PHY, CDCLK helpers. No functional change. Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 12 ++++-------- drivers/gpu/drm/i915/intel_ddi.c | 10 ++++------ drivers/gpu/drm/i915/intel_display.c | 18 +++++++----------- drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 ++-- drivers/gpu/drm/i915/intel_drv.h | 8 ++++---- 5 files changed, 21 insertions(+), 31 deletions(-)