| Message ID | 1459515767-29228-8-git-send-email-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Apr 01, 2016 at 04:02:38PM +0300, Imre Deak wrote: > On SKL/KBL suspend-to-idle (aka freeze/s0ix) is performed with DMC > firmware assistance where the target display power state is DC6. On > Broxton on the other hand we don't use the firmware for this, but rely > instead on a manual DC9 flow. For this we have to uninitialize the > display following the BSpec display uninit sequence, just as during > S3/S4, so make sure we follow this sequence. > > CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_drv.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 020a31c..aa7df10 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -657,7 +657,8 @@ static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation) > > disable_rpm_wakeref_asserts(dev_priv); > > - fw_csr = suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload; > + fw_csr = !IS_BROXTON(dev_priv) && > + suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload; > /* > * In case of firmware assisted context save/restore don't manually > * deinit the power domains. This also means the CSR/DMC firmware will > @@ -837,7 +838,8 @@ static int i915_drm_resume_early(struct drm_device *dev) > > intel_uncore_sanitize(dev); > > - if (!(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload)) > + if (IS_BROXTON(dev_priv) || > + !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload)) > intel_power_domains_init_hw(dev_priv, true); > > out: > -- > 2.5.0 >
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 020a31c..aa7df10 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -657,7 +657,8 @@ static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation) disable_rpm_wakeref_asserts(dev_priv); - fw_csr = suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload; + fw_csr = !IS_BROXTON(dev_priv) && + suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload; /* * In case of firmware assisted context save/restore don't manually * deinit the power domains. This also means the CSR/DMC firmware will @@ -837,7 +838,8 @@ static int i915_drm_resume_early(struct drm_device *dev) intel_uncore_sanitize(dev); - if (!(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload)) + if (IS_BROXTON(dev_priv) || + !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload)) intel_power_domains_init_hw(dev_priv, true); out:
On SKL/KBL suspend-to-idle (aka freeze/s0ix) is performed with DMC firmware assistance where the target display power state is DC6. On Broxton on the other hand we don't use the firmware for this, but rely instead on a manual DC9 flow. For this we have to uninitialize the display following the BSpec display uninit sequence, just as during S3/S4, so make sure we follow this sequence. CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)