From patchwork Tue Apr 5 13:50:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yetunde Adebisi X-Patchwork-Id: 8752021 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 09632C0554 for ; Tue, 5 Apr 2016 13:50:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3BE77203B6 for ; Tue, 5 Apr 2016 13:50:40 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id A8B53203A4 for ; Tue, 5 Apr 2016 13:50:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 187786E184; Tue, 5 Apr 2016 13:50:38 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 29DFB6E184; Tue, 5 Apr 2016 13:50:36 +0000 (UTC) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP; 05 Apr 2016 06:50:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,444,1455004800"; d="scan'208";a="948457742" Received: from unknown (HELO dev_host.localdomain.com) ([10.104.14.133]) by orsmga002.jf.intel.com with ESMTP; 05 Apr 2016 06:50:34 -0700 From: Yetunde Adebisi To: intel-gfx@lists.freedesktop.org Date: Tue, 5 Apr 2016 14:50:25 +0100 Message-Id: <1459864227-8155-2-git-send-email-yetundex.adebisi@intel.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1459864227-8155-1-git-send-email-yetundex.adebisi@intel.com> References: <1459864227-8155-1-git-send-email-yetundex.adebisi@intel.com> Cc: Jani Nikula , isg-gms@eclists.intel.com, dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 1/3] drm/dp: Add definition for Display Control DPCD Registers capability size X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This is used when reading Display Control capability Registers on the sink device. cc: Jani Nikula cc: dri-devel@lists.freedesktop.org Signed-off-by: Yetunde Adebisi --- include/drm/drm_dp_helper.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1252108..92d9a52 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI #define DP_BRANCH_OUI_HEADER_SIZE 0xc #define DP_RECEIVER_CAP_SIZE 0xf #define EDP_PSR_RECEIVER_CAP_SIZE 2 +#define EDP_DISPLAY_CTL_CAP_SIZE 3 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);