From patchwork Thu Apr 7 09:06:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramalingam C X-Patchwork-Id: 8770031 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 71C0DC0553 for ; Thu, 7 Apr 2016 09:15:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 81822201EC for ; Thu, 7 Apr 2016 09:15:09 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 5D761201CD for ; Thu, 7 Apr 2016 09:15:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B3FA26E94C; Thu, 7 Apr 2016 09:15:07 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 53C4C6E37D for ; Thu, 7 Apr 2016 09:15:06 +0000 (UTC) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 07 Apr 2016 02:15:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,448,1455004800"; d="scan'208";a="949973030" Received: from ramaling-desktop.iind.intel.com ([10.223.26.95]) by orsmga002.jf.intel.com with ESMTP; 07 Apr 2016 02:15:03 -0700 From: Ramalingam C To: intel-gfx@lists.freedesktop.org Date: Thu, 7 Apr 2016 14:36:06 +0530 Message-Id: <1460019967-26501-1-git-send-email-ramalingam.c@intel.com> X-Mailer: git-send-email 1.7.9.5 Cc: jani.nikula@intel.com Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Sharing the pixel_format_from_vbt to whole i915 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Shared the function pixel_format_from_vbt for whole display module. Function declaration is added to intel_dsi.h. V2: Moved the function to intel_dsi.c and renamed as per the purpose of the function. Suggested by Jani. Signed-off-by: Ramalingam C Previously reviewed at https://lists.freedesktop.org/archives/intel-gfx/2016-April/091736.html --- drivers/gpu/drm/i915/intel_dsi.c | 18 ++++++++++++++++++ drivers/gpu/drm/i915/intel_dsi.h | 1 + drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 23 +++-------------------- 3 files changed, 22 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 0de74e1..a0f374f 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -46,6 +46,24 @@ static const struct { }, }; +enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) +{ + /* It just so happens the VBT matches register contents. */ + switch (fmt) { + case VID_MODE_FORMAT_RGB888: + return MIPI_DSI_FMT_RGB888; + case VID_MODE_FORMAT_RGB666: + return MIPI_DSI_FMT_RGB666; + case VID_MODE_FORMAT_RGB666_PACKED: + return MIPI_DSI_FMT_RGB666_PACKED; + case VID_MODE_FORMAT_RGB565: + return MIPI_DSI_FMT_RGB565; + default: + MISSING_CASE(fmt); + return MIPI_DSI_FMT_RGB666; + } +} + static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) { struct drm_encoder *encoder = &intel_dsi->base.base; diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h index ec58ead..dabde19 100644 --- a/drivers/gpu/drm/i915/intel_dsi.h +++ b/drivers/gpu/drm/i915/intel_dsi.h @@ -134,5 +134,6 @@ extern void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port); struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id); +enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt); #endif /* _INTEL_DSI_H */ diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c index 8302a97..ca1b016 100644 --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c @@ -412,25 +412,6 @@ static const struct drm_panel_funcs vbt_panel_funcs = { .get_modes = vbt_panel_get_modes, }; -/* XXX: This should be done when parsing the VBT in intel_bios.c */ -static enum mipi_dsi_pixel_format pixel_format_from_vbt(u32 fmt) -{ - /* It just so happens the VBT matches register contents. */ - switch (fmt) { - case VID_MODE_FORMAT_RGB888: - return MIPI_DSI_FMT_RGB888; - case VID_MODE_FORMAT_RGB666: - return MIPI_DSI_FMT_RGB666; - case VID_MODE_FORMAT_RGB666_PACKED: - return MIPI_DSI_FMT_RGB666_PACKED; - case VID_MODE_FORMAT_RGB565: - return MIPI_DSI_FMT_RGB565; - default: - MISSING_CASE(fmt); - return MIPI_DSI_FMT_RGB666; - } -} - struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id) { struct drm_device *dev = intel_dsi->base.base.dev; @@ -455,7 +436,9 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id) intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; intel_dsi->lane_count = mipi_config->lane_cnt + 1; - intel_dsi->pixel_format = pixel_format_from_vbt(mipi_config->videomode_color_format << 7); + intel_dsi->pixel_format = + pixel_format_from_register_bits( + mipi_config->videomode_color_format << 7); bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); intel_dsi->dual_link = mipi_config->dual_link;