diff mbox

[08/10] drm/i915: Move vlv_init_display_clock_gating() to the display power well

Message ID 1460382992-28728-9-git-send-email-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjala April 11, 2016, 1:56 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The registers frobbed by vlv_init_display_clock_gating() libve inside
the disp2d power well, so frobbing them while the power well is down
results in unclaimed register access warning (and of course the values
won't stick). Let's do this setup after we know the power well is
enabled.

It's also worth noting that DSPCLK_GATE_D and CBR1_VLV lose their state
when the power well goes down, but fortunately the values we've been
writing are actually the reset defaults.

MI_ARB_VLV actually retains its value even if the power well was turned
off, we just can't access it while the power well is down.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94164
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c         | 15 ---------------
 drivers/gpu/drm/i915/intel_runtime_pm.c | 13 +++++++++++++
 2 files changed, 13 insertions(+), 15 deletions(-)

Comments

Imre Deak April 12, 2016, 10:25 a.m. UTC | #1 
On ma, 2016-04-11 at 16:56 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The registers frobbed by vlv_init_display_clock_gating() libve inside
> the disp2d power well, so frobbing them while the power well is down
> results in unclaimed register access warning (and of course the
> values
> won't stick). Let's do this setup after we know the power well is
> enabled.
> 
> It's also worth noting that DSPCLK_GATE_D and CBR1_VLV lose their
> state
> when the power well goes down, but fortunately the values we've been
> writing are actually the reset defaults.
> 
> MI_ARB_VLV actually retains its value even if the power well was
> turned
> off, we just can't access it while the power well is down.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94164
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

The spec doesn't say anything about backing power wells, I assume you
checked this manually by reading the regs out while the power well was 
off. Looks ok:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c         | 15 ---------------
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 13 +++++++++++++
>  2 files changed, 13 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 43b24a1f5ee6..c80d044fe082 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6882,23 +6882,10 @@ static void
> ivybridge_init_clock_gating(struct drm_device *dev)
>  	gen6_check_mch_setup(dev);
>  }
>  
> -static void vlv_init_display_clock_gating(struct drm_i915_private
> *dev_priv)
> -{
> -	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
> -
> -	/*
> -	 * Disable trickle feed and enable pnd deadline calculation
> -	 */
> -	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> -	I915_WRITE(CBR1_VLV, 0);
> -}
> -
>  static void valleyview_init_clock_gating(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	vlv_init_display_clock_gating(dev_priv);
> -
>  	/* WaDisableEarlyCull:vlv */
>  	I915_WRITE(_3D_CHICKEN3,
>  		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_
> CULL));
> @@ -6981,8 +6968,6 @@ static void cherryview_init_clock_gating(struct
> drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	vlv_init_display_clock_gating(dev_priv);
> -
>  	/* WaVSRefCountFullforceMissDisable:chv */
>  	/* WaDSRefCountFullforceMissDisable:chv */
>  	I915_WRITE(GEN7_FF_THREAD_MODE,
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 80e8bd4b43b5..8f9797f17991 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -900,6 +900,17 @@ static bool vlv_power_well_enabled(struct
> drm_i915_private *dev_priv,
>  	return enabled;
>  }
>  
> +static void vlv_init_display_clock_gating(struct drm_i915_private
> *dev_priv)
> +{
> +	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
> +
> +	/*
> +	 * Disable trickle feed and enable pnd deadline calculation
> +	 */
> +	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> +	I915_WRITE(CBR1_VLV, 0);
> +}
> +
>  static void vlv_display_power_well_init(struct drm_i915_private
> *dev_priv)
>  {
>  	enum pipe pipe;
> @@ -922,6 +933,8 @@ static void vlv_display_power_well_init(struct
> drm_i915_private *dev_priv)
>  		I915_WRITE(DPLL(pipe), val);
>  	}
>  
> +	vlv_init_display_clock_gating(dev_priv);
> +
>  	spin_lock_irq(&dev_priv->irq_lock);
>  	valleyview_enable_display_irqs(dev_priv);
>  	spin_unlock_irq(&dev_priv->irq_lock);
Ville Syrjala April 12, 2016, 11:51 a.m. UTC | #2 
On Tue, Apr 12, 2016 at 01:25:07PM +0300, Imre Deak wrote:
> On ma, 2016-04-11 at 16:56 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The registers frobbed by vlv_init_display_clock_gating() libve inside
> > the disp2d power well, so frobbing them while the power well is down
> > results in unclaimed register access warning (and of course the
> > values
> > won't stick). Let's do this setup after we know the power well is
> > enabled.
> > 
> > It's also worth noting that DSPCLK_GATE_D and CBR1_VLV lose their
> > state
> > when the power well goes down, but fortunately the values we've been
> > writing are actually the reset defaults.
> > 
> > MI_ARB_VLV actually retains its value even if the power well was
> > turned
> > off, we just can't access it while the power well is down.
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94164
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The spec doesn't say anything about backing power wells, I assume you
> checked this manually by reading the regs out while the power well was 
> off.

Yep.

> Looks ok:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c         | 15 ---------------
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 13 +++++++++++++
> >  2 files changed, 13 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 43b24a1f5ee6..c80d044fe082 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -6882,23 +6882,10 @@ static void
> > ivybridge_init_clock_gating(struct drm_device *dev)
> >  	gen6_check_mch_setup(dev);
> >  }
> >  
> > -static void vlv_init_display_clock_gating(struct drm_i915_private
> > *dev_priv)
> > -{
> > -	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
> > -
> > -	/*
> > -	 * Disable trickle feed and enable pnd deadline calculation
> > -	 */
> > -	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> > -	I915_WRITE(CBR1_VLV, 0);
> > -}
> > -
> >  static void valleyview_init_clock_gating(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  
> > -	vlv_init_display_clock_gating(dev_priv);
> > -
> >  	/* WaDisableEarlyCull:vlv */
> >  	I915_WRITE(_3D_CHICKEN3,
> >  		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_
> > CULL));
> > @@ -6981,8 +6968,6 @@ static void cherryview_init_clock_gating(struct
> > drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  
> > -	vlv_init_display_clock_gating(dev_priv);
> > -
> >  	/* WaVSRefCountFullforceMissDisable:chv */
> >  	/* WaDSRefCountFullforceMissDisable:chv */
> >  	I915_WRITE(GEN7_FF_THREAD_MODE,
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 80e8bd4b43b5..8f9797f17991 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -900,6 +900,17 @@ static bool vlv_power_well_enabled(struct
> > drm_i915_private *dev_priv,
> >  	return enabled;
> >  }
> >  
> > +static void vlv_init_display_clock_gating(struct drm_i915_private
> > *dev_priv)
> > +{
> > +	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
> > +
> > +	/*
> > +	 * Disable trickle feed and enable pnd deadline calculation
> > +	 */
> > +	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> > +	I915_WRITE(CBR1_VLV, 0);
> > +}
> > +
> >  static void vlv_display_power_well_init(struct drm_i915_private
> > *dev_priv)
> >  {
> >  	enum pipe pipe;
> > @@ -922,6 +933,8 @@ static void vlv_display_power_well_init(struct
> > drm_i915_private *dev_priv)
> >  		I915_WRITE(DPLL(pipe), val);
> >  	}
> >  
> > +	vlv_init_display_clock_gating(dev_priv);
> > +
> >  	spin_lock_irq(&dev_priv->irq_lock);
> >  	valleyview_enable_display_irqs(dev_priv);
> >  	spin_unlock_irq(&dev_priv->irq_lock);
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 43b24a1f5ee6..c80d044fe082 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6882,23 +6882,10 @@  static void ivybridge_init_clock_gating(struct drm_device *dev)
 	gen6_check_mch_setup(dev);
 }
 
-static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
-{
-	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
-
-	/*
-	 * Disable trickle feed and enable pnd deadline calculation
-	 */
-	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
-	I915_WRITE(CBR1_VLV, 0);
-}
-
 static void valleyview_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	vlv_init_display_clock_gating(dev_priv);
-
 	/* WaDisableEarlyCull:vlv */
 	I915_WRITE(_3D_CHICKEN3,
 		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
@@ -6981,8 +6968,6 @@  static void cherryview_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	vlv_init_display_clock_gating(dev_priv);
-
 	/* WaVSRefCountFullforceMissDisable:chv */
 	/* WaDSRefCountFullforceMissDisable:chv */
 	I915_WRITE(GEN7_FF_THREAD_MODE,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 80e8bd4b43b5..8f9797f17991 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -900,6 +900,17 @@  static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
 	return enabled;
 }
 
+static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
+{
+	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
+
+	/*
+	 * Disable trickle feed and enable pnd deadline calculation
+	 */
+	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
+	I915_WRITE(CBR1_VLV, 0);
+}
+
 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 {
 	enum pipe pipe;
@@ -922,6 +933,8 @@  static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 		I915_WRITE(DPLL(pipe), val);
 	}
 
+	vlv_init_display_clock_gating(dev_priv);
+
 	spin_lock_irq(&dev_priv->irq_lock);
 	valleyview_enable_display_irqs(dev_priv);
 	spin_unlock_irq(&dev_priv->irq_lock);