diff mbox

[v2,07/10] drm/i915: Undiplicate VLV signal level code

Message ID 1460569673-13694-8-git-send-email-ander.conselvan.de.oliveira@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ander Conselvan de Oliveira April 13, 2016, 5:47 p.m. UTC
The logic for setting signal levels is used for both HDMI and DP with
small variations. But it is similar enough to put behind a function
called from the encoders.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |  4 ++++
 drivers/gpu/drm/i915/intel_dp.c       | 43 ++++++++++++-----------------------
 drivers/gpu/drm/i915/intel_dpio_phy.c | 26 +++++++++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c     | 14 ++++--------
 4 files changed, 49 insertions(+), 38 deletions(-)

Comments

jim.bride@linux.intel.com April 19, 2016, 8:37 p.m. UTC | #1
On Wed, Apr 13, 2016 at 08:47:50PM +0300, Ander Conselvan de Oliveira wrote:
> The logic for setting signal levels is used for both HDMI and DP with
> small variations. But it is similar enough to put behind a function
> called from the encoders.
> 
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  4 ++++
>  drivers/gpu/drm/i915/intel_dp.c       | 43 ++++++++++++-----------------------
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 26 +++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c     | 14 ++++--------
>  4 files changed, 49 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 85c0610..f2481a2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3565,6 +3565,10 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
>  void chv_phy_release_cl2_override(struct intel_encoder *encoder);
>  void chv_phy_post_disable(struct intel_encoder *encoder);
>  
> +void vlv_set_phy_signal_level(struct intel_encoder *encoder,
> +			      u32 demph_reg_value, u32 preemph_reg_value,
> +			      u32 uniqtranscale_reg_value, u32 tx3_demph);
> +
>  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
>  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index cdacd8b..3e42355 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3009,16 +3009,10 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>  
>  static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
>  {
> -	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> -	struct intel_crtc *intel_crtc =
> -		to_intel_crtc(dport->base.base.crtc);
> +	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>  	unsigned long demph_reg_value, preemph_reg_value,
>  		uniqtranscale_reg_value;
>  	uint8_t train_set = intel_dp->train_set[0];
> -	enum dpio_channel port = vlv_dport_to_channel(dport);
> -	int pipe = intel_crtc->pipe;
>  
>  	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
>  	case DP_TRAIN_PRE_EMPH_LEVEL_0:
> @@ -3093,16 +3087,8 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
>  		return 0;
>  	}
>  
> -	mutex_lock(&dev_priv->sb_lock);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
> -			 uniqtranscale_reg_value);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
> -	mutex_unlock(&dev_priv->sb_lock);
> +	vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
> +				 uniqtranscale_reg_value, 0);
>  
>  	return 0;
>  }
> @@ -4285,17 +4271,6 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
>  		intel_dp->compliance_test_type = 0;
>  		intel_dp->compliance_test_data = 0;
>  
> -		/*
> -		 * If we were in MST mode, and device is not there,
> -		 * get out of MST mode
> -		 */
> -		if (intel_dp->is_mst) {
> -			DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
> -				      intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
> -			intel_dp->is_mst = false;
> -			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
> -							intel_dp->is_mst);
> -		}
>  		goto out;
>  	}
>  
> @@ -4355,6 +4330,18 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
>  out:
>  	if (status != connector_status_connected) {
>  		intel_dp_unset_edid(intel_dp);
> +
> +		/*
> +		 * If we were in MST mode, and device is not there,
> +		 * get out of MST mode
> +		 */
> +		if (intel_dp->is_mst) {
> +			DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
> +				      intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
> +			intel_dp->is_mst = false;
> +			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
> +							intel_dp->is_mst);
> +		}

The two hunks above seem unrelated to what the patch set is trying to do and
would break DP MST again. ;)

Jim


>  	}
>  
>  	intel_display_power_put(to_i915(dev), power_domain);
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 2400554..d9e6482 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -369,3 +369,29 @@ void chv_phy_post_disable(struct intel_encoder *encoder)
>  	 */
>  	chv_phy_powergate_lanes(encoder, false, 0x0);
>  }
> +
> +void vlv_set_phy_signal_level(struct intel_encoder *encoder,
> +			      u32 demph_reg_value, u32 preemph_reg_value,
> +			      u32 uniqtranscale_reg_value, u32 tx3_demph)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> +	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> +	enum dpio_channel port = vlv_dport_to_channel(dport);
> +	int pipe = intel_crtc->pipe;
> +
> +	mutex_lock(&dev_priv->sb_lock);
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
> +			 uniqtranscale_reg_value);
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
> +
> +	if (tx3_demph)
> +		vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);
> +
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
> +	mutex_unlock(&dev_priv->sb_lock);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index f424af5..9386772 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1601,21 +1601,15 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
>  	val |= 0x001000c4;
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
>  
> -	/* HDMI 1.0V-2dB */
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
> -
>  	/* Program lane clock */
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
>  	mutex_unlock(&dev_priv->sb_lock);
>  
> +	/* HDMI 1.0V-2dB */
> +	vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
> +				 0x2b247878);
> +
>  	intel_hdmi->set_infoframes(&encoder->base,
>  				   intel_crtc->config->has_hdmi_sink,
>  				   adjusted_mode);
> -- 
> 2.4.11
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
jim.bride@linux.intel.com April 19, 2016, 8:45 p.m. UTC | #2
On Tue, Apr 19, 2016 at 01:37:26PM -0700, Jim Bride wrote:
> On Wed, Apr 13, 2016 at 08:47:50PM +0300, Ander Conselvan de Oliveira wrote:

Same typo in this patch's subject ('Undiplicate') as the previous one.

Jim


> > The logic for setting signal levels is used for both HDMI and DP with
> > small variations. But it is similar enough to put behind a function
> > called from the encoders.
> > 
> > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h       |  4 ++++
> >  drivers/gpu/drm/i915/intel_dp.c       | 43 ++++++++++++-----------------------
> >  drivers/gpu/drm/i915/intel_dpio_phy.c | 26 +++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_hdmi.c     | 14 ++++--------
> >  4 files changed, 49 insertions(+), 38 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 85c0610..f2481a2 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -3565,6 +3565,10 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
> >  void chv_phy_release_cl2_override(struct intel_encoder *encoder);
> >  void chv_phy_post_disable(struct intel_encoder *encoder);
> >  
> > +void vlv_set_phy_signal_level(struct intel_encoder *encoder,
> > +			      u32 demph_reg_value, u32 preemph_reg_value,
> > +			      u32 uniqtranscale_reg_value, u32 tx3_demph);
> > +
> >  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
> >  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index cdacd8b..3e42355 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3009,16 +3009,10 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
> >  
> >  static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
> >  {
> > -	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> > -	struct drm_i915_private *dev_priv = dev->dev_private;
> > -	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> > -	struct intel_crtc *intel_crtc =
> > -		to_intel_crtc(dport->base.base.crtc);
> > +	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> >  	unsigned long demph_reg_value, preemph_reg_value,
> >  		uniqtranscale_reg_value;
> >  	uint8_t train_set = intel_dp->train_set[0];
> > -	enum dpio_channel port = vlv_dport_to_channel(dport);
> > -	int pipe = intel_crtc->pipe;
> >  
> >  	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
> >  	case DP_TRAIN_PRE_EMPH_LEVEL_0:
> > @@ -3093,16 +3087,8 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
> >  		return 0;
> >  	}
> >  
> > -	mutex_lock(&dev_priv->sb_lock);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
> > -			 uniqtranscale_reg_value);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
> > -	mutex_unlock(&dev_priv->sb_lock);
> > +	vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
> > +				 uniqtranscale_reg_value, 0);
> >  
> >  	return 0;
> >  }
> > @@ -4285,17 +4271,6 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
> >  		intel_dp->compliance_test_type = 0;
> >  		intel_dp->compliance_test_data = 0;
> >  
> > -		/*
> > -		 * If we were in MST mode, and device is not there,
> > -		 * get out of MST mode
> > -		 */
> > -		if (intel_dp->is_mst) {
> > -			DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
> > -				      intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
> > -			intel_dp->is_mst = false;
> > -			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
> > -							intel_dp->is_mst);
> > -		}
> >  		goto out;
> >  	}
> >  
> > @@ -4355,6 +4330,18 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
> >  out:
> >  	if (status != connector_status_connected) {
> >  		intel_dp_unset_edid(intel_dp);
> > +
> > +		/*
> > +		 * If we were in MST mode, and device is not there,
> > +		 * get out of MST mode
> > +		 */
> > +		if (intel_dp->is_mst) {
> > +			DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
> > +				      intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
> > +			intel_dp->is_mst = false;
> > +			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
> > +							intel_dp->is_mst);
> > +		}
> 
> The two hunks above seem unrelated to what the patch set is trying to do and
> would break DP MST again. ;)
> 
> Jim
> 
> 
> >  	}
> >  
> >  	intel_display_power_put(to_i915(dev), power_domain);
> > diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > index 2400554..d9e6482 100644
> > --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> > +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > @@ -369,3 +369,29 @@ void chv_phy_post_disable(struct intel_encoder *encoder)
> >  	 */
> >  	chv_phy_powergate_lanes(encoder, false, 0x0);
> >  }
> > +
> > +void vlv_set_phy_signal_level(struct intel_encoder *encoder,
> > +			      u32 demph_reg_value, u32 preemph_reg_value,
> > +			      u32 uniqtranscale_reg_value, u32 tx3_demph)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> > +	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> > +	enum dpio_channel port = vlv_dport_to_channel(dport);
> > +	int pipe = intel_crtc->pipe;
> > +
> > +	mutex_lock(&dev_priv->sb_lock);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
> > +			 uniqtranscale_reg_value);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
> > +
> > +	if (tx3_demph)
> > +		vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);
> > +
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
> > +	mutex_unlock(&dev_priv->sb_lock);
> > +}
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> > index f424af5..9386772 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -1601,21 +1601,15 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
> >  	val |= 0x001000c4;
> >  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
> >  
> > -	/* HDMI 1.0V-2dB */
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
> > -
> >  	/* Program lane clock */
> >  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
> >  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
> >  	mutex_unlock(&dev_priv->sb_lock);
> >  
> > +	/* HDMI 1.0V-2dB */
> > +	vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
> > +				 0x2b247878);
> > +
> >  	intel_hdmi->set_infoframes(&encoder->base,
> >  				   intel_crtc->config->has_hdmi_sink,
> >  				   adjusted_mode);
> > -- 
> > 2.4.11
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Ander Conselvan de Oliveira April 20, 2016, 5:23 a.m. UTC | #3
On Tue, 2016-04-19 at 13:37 -0700, Jim Bride wrote:
> On Wed, Apr 13, 2016 at 08:47:50PM +0300, Ander Conselvan de Oliveira wrote:

> > The logic for setting signal levels is used for both HDMI and DP with

> > small variations. But it is similar enough to put behind a function

> > called from the encoders.

> > 

> > Signed-off-by: Ander Conselvan de Oliveira <

> > ander.conselvan.de.oliveira@intel.com>

> > ---

> >  drivers/gpu/drm/i915/i915_drv.h       |  4 ++++

> >  drivers/gpu/drm/i915/intel_dp.c       | 43 ++++++++++++--------------------

> > ---

> >  drivers/gpu/drm/i915/intel_dpio_phy.c | 26 +++++++++++++++++++++

> >  drivers/gpu/drm/i915/intel_hdmi.c     | 14 ++++--------

> >  4 files changed, 49 insertions(+), 38 deletions(-)

> > 

> > diff --git a/drivers/gpu/drm/i915/i915_drv.h

> > b/drivers/gpu/drm/i915/i915_drv.h

> > index 85c0610..f2481a2 100644

> > --- a/drivers/gpu/drm/i915/i915_drv.h

> > +++ b/drivers/gpu/drm/i915/i915_drv.h

> > @@ -3565,6 +3565,10 @@ void chv_phy_pre_encoder_enable(struct intel_encoder

> > *encoder);

> >  void chv_phy_release_cl2_override(struct intel_encoder *encoder);

> >  void chv_phy_post_disable(struct intel_encoder *encoder);

> >  

> > +void vlv_set_phy_signal_level(struct intel_encoder *encoder,

> > +			      u32 demph_reg_value, u32 preemph_reg_value,

> > +			      u32 uniqtranscale_reg_value, u32 tx3_demph);

> > +

> >  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);

> >  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);

> >  

> > diff --git a/drivers/gpu/drm/i915/intel_dp.c

> > b/drivers/gpu/drm/i915/intel_dp.c

> > index cdacd8b..3e42355 100644

> > --- a/drivers/gpu/drm/i915/intel_dp.c

> > +++ b/drivers/gpu/drm/i915/intel_dp.c

> > @@ -3009,16 +3009,10 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp,

> > uint8_t voltage_swing)

> >  

> >  static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)

> >  {

> > -	struct drm_device *dev = intel_dp_to_dev(intel_dp);

> > -	struct drm_i915_private *dev_priv = dev->dev_private;

> > -	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);

> > -	struct intel_crtc *intel_crtc =

> > -		to_intel_crtc(dport->base.base.crtc);

> > +	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

> >  	unsigned long demph_reg_value, preemph_reg_value,

> >  		uniqtranscale_reg_value;

> >  	uint8_t train_set = intel_dp->train_set[0];

> > -	enum dpio_channel port = vlv_dport_to_channel(dport);

> > -	int pipe = intel_crtc->pipe;

> >  

> >  	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {

> >  	case DP_TRAIN_PRE_EMPH_LEVEL_0:

> > @@ -3093,16 +3087,8 @@ static uint32_t vlv_signal_levels(struct intel_dp

> > *intel_dp)

> >  		return 0;

> >  	}

> >  

> > -	mutex_lock(&dev_priv->sb_lock);

> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);

> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);

> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),

> > -			 uniqtranscale_reg_value);

> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);

> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);

> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port),

> > preemph_reg_value);

> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);

> > -	mutex_unlock(&dev_priv->sb_lock);

> > +	vlv_set_phy_signal_level(encoder, demph_reg_value,

> > preemph_reg_value,

> > +				 uniqtranscale_reg_value, 0);

> >  

> >  	return 0;

> >  }

> > @@ -4285,17 +4271,6 @@ intel_dp_long_pulse(struct intel_connector

> > *intel_connector)

> >  		intel_dp->compliance_test_type = 0;

> >  		intel_dp->compliance_test_data = 0;

> >  

> > -		/*

> > -		 * If we were in MST mode, and device is not there,

> > -		 * get out of MST mode

> > -		 */

> > -		if (intel_dp->is_mst) {

> > -			DRM_DEBUG_KMS("MST device may have disappeared %d

> > vs %d\n",

> > -				      intel_dp->is_mst, intel_dp

> > ->mst_mgr.mst_state);

> > -			intel_dp->is_mst = false;

> > -			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,

> > -							intel_dp->is_mst);

> > -		}

> >  		goto out;

> >  	}

> >  

> > @@ -4355,6 +4330,18 @@ intel_dp_long_pulse(struct intel_connector

> > *intel_connector)

> >  out:

> >  	if (status != connector_status_connected) {

> >  		intel_dp_unset_edid(intel_dp);

> > +

> > +		/*

> > +		 * If we were in MST mode, and device is not there,

> > +		 * get out of MST mode

> > +		 */

> > +		if (intel_dp->is_mst) {

> > +			DRM_DEBUG_KMS("MST device may have disappeared %d

> > vs %d\n",

> > +				      intel_dp->is_mst, intel_dp

> > ->mst_mgr.mst_state);

> > +			intel_dp->is_mst = false;

> > +			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,

> > +							intel_dp->is_mst);

> > +		}

> 

> The two hunks above seem unrelated to what the patch set is trying to do and

> would break DP MST again. ;)


I mixed things up when rebasing on top of your changes. I remember fixing that,
but alas, I didn't. 

Ander


> 

> Jim

> 

> 

> >  	}

> >  

> >  	intel_display_power_put(to_i915(dev), power_domain);

> > diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c

> > b/drivers/gpu/drm/i915/intel_dpio_phy.c

> > index 2400554..d9e6482 100644

> > --- a/drivers/gpu/drm/i915/intel_dpio_phy.c

> > +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c

> > @@ -369,3 +369,29 @@ void chv_phy_post_disable(struct intel_encoder

> > *encoder)

> >  	 */

> >  	chv_phy_powergate_lanes(encoder, false, 0x0);

> >  }

> > +

> > +void vlv_set_phy_signal_level(struct intel_encoder *encoder,

> > +			      u32 demph_reg_value, u32 preemph_reg_value,

> > +			      u32 uniqtranscale_reg_value, u32 tx3_demph)

> > +{

> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

> > +	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);

> > +	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);

> > +	enum dpio_channel port = vlv_dport_to_channel(dport);

> > +	int pipe = intel_crtc->pipe;

> > +

> > +	mutex_lock(&dev_priv->sb_lock);

> > +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);

> > +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);

> > +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),

> > +			 uniqtranscale_reg_value);

> > +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);

> > +

> > +	if (tx3_demph)

> > +		vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port),

> > tx3_demph);

> > +

> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);

> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port),

> > preemph_reg_value);

> > +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port),

> > DPIO_TX_OCALINIT_EN);

> > +	mutex_unlock(&dev_priv->sb_lock);

> > +}

> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c

> > b/drivers/gpu/drm/i915/intel_hdmi.c

> > index f424af5..9386772 100644

> > --- a/drivers/gpu/drm/i915/intel_hdmi.c

> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c

> > @@ -1601,21 +1601,15 @@ static void vlv_hdmi_pre_enable(struct intel_encoder

> > *encoder)

> >  	val |= 0x001000c4;

> >  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);

> >  

> > -	/* HDMI 1.0V-2dB */

> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);

> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);

> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);

> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);

> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);

> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);

> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);

> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port),

> > DPIO_TX_OCALINIT_EN);

> > -

> >  	/* Program lane clock */

> >  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);

> >  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);

> >  	mutex_unlock(&dev_priv->sb_lock);

> >  

> > +	/* HDMI 1.0V-2dB */

> > +	vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000,

> > 0x5578b83a,

> > +				 0x2b247878);

> > +

> >  	intel_hdmi->set_infoframes(&encoder->base,

> >  				   intel_crtc->config->has_hdmi_sink,

> >  				   adjusted_mode);
---------------------------------------------------------------------
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diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 85c0610..f2481a2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3565,6 +3565,10 @@  void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
 void chv_phy_post_disable(struct intel_encoder *encoder);
 
+void vlv_set_phy_signal_level(struct intel_encoder *encoder,
+			      u32 demph_reg_value, u32 preemph_reg_value,
+			      u32 uniqtranscale_reg_value, u32 tx3_demph);
+
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index cdacd8b..3e42355 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3009,16 +3009,10 @@  intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 
 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
 {
-	struct drm_device *dev = intel_dp_to_dev(intel_dp);
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
-	struct intel_crtc *intel_crtc =
-		to_intel_crtc(dport->base.base.crtc);
+	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	unsigned long demph_reg_value, preemph_reg_value,
 		uniqtranscale_reg_value;
 	uint8_t train_set = intel_dp->train_set[0];
-	enum dpio_channel port = vlv_dport_to_channel(dport);
-	int pipe = intel_crtc->pipe;
 
 	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
 	case DP_TRAIN_PRE_EMPH_LEVEL_0:
@@ -3093,16 +3087,8 @@  static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
 		return 0;
 	}
 
-	mutex_lock(&dev_priv->sb_lock);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
-			 uniqtranscale_reg_value);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
-	mutex_unlock(&dev_priv->sb_lock);
+	vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
+				 uniqtranscale_reg_value, 0);
 
 	return 0;
 }
@@ -4285,17 +4271,6 @@  intel_dp_long_pulse(struct intel_connector *intel_connector)
 		intel_dp->compliance_test_type = 0;
 		intel_dp->compliance_test_data = 0;
 
-		/*
-		 * If we were in MST mode, and device is not there,
-		 * get out of MST mode
-		 */
-		if (intel_dp->is_mst) {
-			DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
-				      intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
-			intel_dp->is_mst = false;
-			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
-							intel_dp->is_mst);
-		}
 		goto out;
 	}
 
@@ -4355,6 +4330,18 @@  intel_dp_long_pulse(struct intel_connector *intel_connector)
 out:
 	if (status != connector_status_connected) {
 		intel_dp_unset_edid(intel_dp);
+
+		/*
+		 * If we were in MST mode, and device is not there,
+		 * get out of MST mode
+		 */
+		if (intel_dp->is_mst) {
+			DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
+				      intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
+			intel_dp->is_mst = false;
+			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
+							intel_dp->is_mst);
+		}
 	}
 
 	intel_display_power_put(to_i915(dev), power_domain);
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 2400554..d9e6482 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -369,3 +369,29 @@  void chv_phy_post_disable(struct intel_encoder *encoder)
 	 */
 	chv_phy_powergate_lanes(encoder, false, 0x0);
 }
+
+void vlv_set_phy_signal_level(struct intel_encoder *encoder,
+			      u32 demph_reg_value, u32 preemph_reg_value,
+			      u32 uniqtranscale_reg_value, u32 tx3_demph)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
+	enum dpio_channel port = vlv_dport_to_channel(dport);
+	int pipe = intel_crtc->pipe;
+
+	mutex_lock(&dev_priv->sb_lock);
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
+			 uniqtranscale_reg_value);
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
+
+	if (tx3_demph)
+		vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);
+
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
+	mutex_unlock(&dev_priv->sb_lock);
+}
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index f424af5..9386772 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1601,21 +1601,15 @@  static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
 	val |= 0x001000c4;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
 
-	/* HDMI 1.0V-2dB */
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
-
 	/* Program lane clock */
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
 	mutex_unlock(&dev_priv->sb_lock);
 
+	/* HDMI 1.0V-2dB */
+	vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
+				 0x2b247878);
+
 	intel_hdmi->set_infoframes(&encoder->base,
 				   intel_crtc->config->has_hdmi_sink,
 				   adjusted_mode);