From patchwork Tue Apr 19 06:49:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 8877141 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id F0C34BF29F for ; Tue, 19 Apr 2016 06:49:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8B10620268 for ; Tue, 19 Apr 2016 06:49:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E1D352026D for ; Tue, 19 Apr 2016 06:49:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A44AF6E6AB; Tue, 19 Apr 2016 06:49:39 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) by gabe.freedesktop.org (Postfix) with ESMTPS id E2EE86E6A7 for ; Tue, 19 Apr 2016 06:49:36 +0000 (UTC) Received: by mail-wm0-x241.google.com with SMTP id n3so2252092wmn.1 for ; Mon, 18 Apr 2016 23:49:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=JejbDj0T7HIvF4GtfUsRRzhv5/gAaqMCSSGIKuroGJQ=; b=ORnlPdD1SfR+/vG/7TdP20egclEbfB789ScmAreKyq0XzAOOpex5kVOQQ0gzDK3fpJ pFOM3X6zfUiWajcAMCRbpkGfMk0Ph0wHkx5W4IRnFq/Ct8hmZsR/oWfVGi7YTI2ovgCK rMeMcmezIif6k0Gv54uJBW1X5cXxHly9f1JVG0CMffLiBhdlManzNpAIzLVQMuj2ZIlx 6Rssnsfi+3xj3iCgeuRGGyIish0zMmqW3xjDnSzj7EsQb6m/enRjAmLYQvejIt7W5ZZo 21/16a7NSTRb86tlVAGcB938Cxosyi6HK299Xn27DReMu9NKmnNzcNm4lr0Os149jOz4 B1KQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=JejbDj0T7HIvF4GtfUsRRzhv5/gAaqMCSSGIKuroGJQ=; b=kEF/gPPA7vIkFYUcM3UJzy9pq0NSGLppwq5zvwiL5IDasy59UGRXrd/fIloYnM1rmG 70zTqx2JuMZknMfEACaaYUiJzf2ppLW/UZK1P0t5kkb7ZoSHSsO8iZhEzhMKDzabByY4 p6LksnMMiZ7i6dTgi+4qQvnaA/pQ4X87mVozyvqhZ1w88sf0lDygKsYQpZLw96YEtjsw 7cJ9+nqPJsOAGSDIr7VzQgkFXzkIdcEiQaz/VZT//lY7/syFrdVFBLMp0HoyAap+6kYB PEavKFg+aud/rQQ2LJK9wgMtOk9WMNh60tlLCaHIIMfaYtLcy8UZ4ED+oeohHlkkZsUD AxrQ== X-Gm-Message-State: AOPr4FXliVEjq/Aa3iPePY/hScrUu/aWOwT0XLJlxitXRFE7kOMLGw2fCpzglXi7fHSKAw== X-Received: by 10.28.31.22 with SMTP id f22mr1744359wmf.103.1461048575034; Mon, 18 Apr 2016 23:49:35 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id w10sm56479720wjz.9.2016.04.18.23.49.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Apr 2016 23:49:33 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org, Tvrtko Ursulin Date: Tue, 19 Apr 2016 07:49:16 +0100 Message-Id: <1461048560-31983-6-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.8.0.rc3 In-Reply-To: <1461048560-31983-1-git-send-email-chris@chris-wilson.co.uk> References: <1460721275-1001-1-git-send-email-tvrtko.ursulin@linux.intel.com> <1461048560-31983-1-git-send-email-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 5/9] drm/i915: Rearrange switch_context to load the aliasing ppgtt on first use X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The code to switch_mm() is already handled by i915_switch_context(), the only difference required to setup the aliasing ppgtt is that we need to emit te switch_mm() on the first context, i.e. when transitioning from engine->last_context == NULL. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/i915_gem.c | 28 --------------------- drivers/gpu/drm/i915/i915_gem_context.c | 43 +++++++++------------------------ drivers/gpu/drm/i915/i915_gem_gtt.c | 13 ---------- drivers/gpu/drm/i915/i915_gem_gtt.h | 1 - 5 files changed, 12 insertions(+), 74 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4c55f480f60b..77becfd5a09d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3125,7 +3125,6 @@ int __must_check i915_gem_context_init(struct drm_device *dev); void i915_gem_context_fini(struct drm_device *dev); void i915_gem_context_reset(struct drm_device *dev); int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); -int i915_gem_context_enable(struct drm_i915_gem_request *req); void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); int i915_switch_context(struct drm_i915_gem_request *req); struct intel_context * diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index fd9a36badb45..4057c0febccd 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4245,34 +4245,6 @@ i915_gem_init_hw(struct drm_device *dev) } } - /* Now it is safe to go back round and do everything else: */ - for_each_engine(engine, dev_priv) { - struct drm_i915_gem_request *req; - - req = i915_gem_request_alloc(engine, NULL); - if (IS_ERR(req)) { - ret = PTR_ERR(req); - break; - } - - ret = i915_ppgtt_init_ring(req); - if (ret) - goto err_request; - - ret = i915_gem_context_enable(req); - if (ret) - goto err_request; - -err_request: - i915_add_request_no_flush(req); - if (ret) { - DRM_ERROR("Failed to enable %s, error=%d\n", - engine->name, ret); - i915_gem_cleanup_engines(dev); - break; - } - } - out: intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); return ret; diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 6870556a180b..cf84138de4ec 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -471,27 +471,6 @@ void i915_gem_context_fini(struct drm_device *dev) dev_priv->kernel_context = NULL; } -int i915_gem_context_enable(struct drm_i915_gem_request *req) -{ - struct intel_engine_cs *engine = req->engine; - int ret; - - if (i915.enable_execlists) { - if (engine->init_context == NULL) - return 0; - - ret = engine->init_context(req); - } else - ret = i915_switch_context(req); - - if (ret) { - DRM_ERROR("ring init context: %d\n", ret); - return ret; - } - - return 0; -} - static int context_idr_cleanup(int id, void *p, void *data) { struct intel_context *ctx = p; @@ -661,7 +640,7 @@ static bool needs_pd_load_pre(struct intel_engine_cs *engine, struct intel_context *to) { if (!to->ppgtt) - return false; + return engine->last_context == NULL; if (engine->last_context == to && !(intel_engine_flag(engine) & to->ppgtt->pd_dirty_rings)) @@ -724,6 +703,7 @@ static int do_rcs_switch(struct drm_i915_gem_request *req) { struct intel_context *to = req->ctx; struct intel_engine_cs *engine = req->engine; + struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt; struct intel_context *from; u32 hw_flags; int ret, i; @@ -765,7 +745,7 @@ static int do_rcs_switch(struct drm_i915_gem_request *req) * Register Immediate commands in Ring Buffer before submitting * a context."*/ trace_switch_mm(engine, to); - ret = to->ppgtt->switch_mm(to->ppgtt, req); + ret = ppgtt->switch_mm(ppgtt, req); if (ret) goto unpin_out; } @@ -776,8 +756,7 @@ static int do_rcs_switch(struct drm_i915_gem_request *req) * space. This means we must enforce that a page table load * occur when this occurs. */ hw_flags = MI_RESTORE_INHIBIT; - else if (to->ppgtt && - intel_engine_flag(engine) & to->ppgtt->pd_dirty_rings) + else if (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings) hw_flags = MI_FORCE_RESTORE; else hw_flags = 0; @@ -822,7 +801,7 @@ static int do_rcs_switch(struct drm_i915_gem_request *req) */ if (needs_pd_load_post(to, hw_flags)) { trace_switch_mm(engine, to); - ret = to->ppgtt->switch_mm(to->ppgtt, req); + ret = ppgtt->switch_mm(to->ppgtt, req); /* The hardware context switch is emitted, but we haven't * actually changed the state - so it's probably safe to bail * here. Still, let the user know something dangerous has @@ -832,8 +811,8 @@ static int do_rcs_switch(struct drm_i915_gem_request *req) return ret; } - if (to->ppgtt) - to->ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); + if (ppgtt) + ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); for (i = 0; i < MAX_L3_SLICES; i++) { if (!(to->remap_slice & (1<ctx; if (needs_pd_load_pre(engine, to)) { + struct i915_hw_ppgtt *ppgtt; int ret; + ppgtt = to->ppgtt ?: to_i915(req)->mm.aliasing_ppgtt; + trace_switch_mm(engine, to); - ret = to->ppgtt->switch_mm(to->ppgtt, req); + ret = ppgtt->switch_mm(ppgtt, req); if (ret) return ret; - /* Doing a PD load always reloads the page dirs */ - to->ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); + ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); } if (to != engine->last_context) { diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 780e3ad3ca10..50bdba5cb6d2 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2180,19 +2180,6 @@ int i915_ppgtt_init_hw(struct drm_device *dev) return 0; } -int i915_ppgtt_init_ring(struct drm_i915_gem_request *req) -{ - struct i915_hw_ppgtt *ppgtt = to_i915(req)->mm.aliasing_ppgtt; - - if (i915.enable_execlists) - return 0; - - if (!ppgtt) - return 0; - - return ppgtt->switch_mm(ppgtt, req); -} - struct i915_hw_ppgtt * i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) { diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index d7dd3d8a8758..333a2fc62b43 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -519,7 +519,6 @@ void i915_ggtt_cleanup_hw(struct drm_device *dev); int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt); int i915_ppgtt_init_hw(struct drm_device *dev); -int i915_ppgtt_init_ring(struct drm_i915_gem_request *req); void i915_ppgtt_release(struct kref *kref); struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv);