From patchwork Tue Apr 19 06:49:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 8877161 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7BB619F443 for ; Tue, 19 Apr 2016 06:49:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 369782026F for ; Tue, 19 Apr 2016 06:49:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 20FC920270 for ; Tue, 19 Apr 2016 06:49:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1BA7D6E6AC; Tue, 19 Apr 2016 06:49:43 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id B955B6E6AC for ; Tue, 19 Apr 2016 06:49:39 +0000 (UTC) Received: by mail-wm0-x244.google.com with SMTP id n3so2252291wmn.1 for ; Mon, 18 Apr 2016 23:49:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=YcVG7VpxmZof9SISddE/BwSkwP3I5cq38WCjZ7tFGPg=; b=V0pUifwLeICFowI13uD0u8ZAP9XnMbyH0Ccx5MhdpFzftptseTVoxh9S8yMoG167Km 7CTPRYctNnthyNu/bMlfmg0O4MYGDxS4r02oNFb1+dwSgGk59nbzQI2L+ONExFQK7mUD kiFUcJH6yzrKHyfwJMtI+w+Kw8YBcYtSSKUWGo/tAy1zeP5Fr6HbjPdIDe0ToV0GwXEW lzBRnbJhNbh8J3kFb9Rf37TUmLSAwThj/RGyN2QlEJ+KHSgsGPh1hib8B6NNOzKiWLkp RgZocHlEp2cpk/NqZmKXgmP/KNCcdPJu0udwC0Da4xlqvN8j1wyfHiIvCHlzLozxL7s/ RKfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=YcVG7VpxmZof9SISddE/BwSkwP3I5cq38WCjZ7tFGPg=; b=Y/T1Jdr49WAZw7Lm3EUEDQqYipUz2rM0upFPNMPmUvfj2+g1sj7SRhAh9P7yrNKl5R zc5+3AyRfO8/UYs68okidJP3FyCU96qI6b01d+ou5frWMCr+fCc+WWykHOiQ4+0NfYmJ xMAlEATpmzhQ1q229TIgVYNdw0U4AA3gkhrNqquVZPqYL4b9PcSGbxagtHqe4Cbv1N7g q0dLjLpCJrPFQjagxC41m+XqBrZ+YgaY5rIHRzLJbgtx3zZi95vkDb0ePEzhjzwnmtuC 3Isr61trJJXtqZ3ZYLyYJW8qHnVSFfu1GtQI7t6zfolJlQL8SGetNHZg+djujskuhWay v27A== X-Gm-Message-State: AOPr4FWuD9gZVreyJwWayBjy3AaOFqmQJkqC8CqiGLkYgTH9IGm84SAKdXjZk3OpuVq4rQ== X-Received: by 10.28.73.66 with SMTP id w63mr1775775wma.53.1461048577371; Mon, 18 Apr 2016 23:49:37 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id w10sm56479720wjz.9.2016.04.18.23.49.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Apr 2016 23:49:36 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org, Tvrtko Ursulin Date: Tue, 19 Apr 2016 07:49:18 +0100 Message-Id: <1461048560-31983-8-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.8.0.rc3 In-Reply-To: <1461048560-31983-1-git-send-email-chris@chris-wilson.co.uk> References: <1460721275-1001-1-git-send-email-tvrtko.ursulin@linux.intel.com> <1461048560-31983-1-git-send-email-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 7/9] drm/i915: Move the magical deferred context allocation into the request X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We can hide more details of execlists from higher level code by removing the explicit call to create an execlist context into its first use. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 -------- drivers/gpu/drm/i915/intel_lrc.c | 21 ++++++++++++++------- drivers/gpu/drm/i915/intel_lrc.h | 2 -- 3 files changed, 14 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 0d210c383487..3da5978ac0f7 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1080,14 +1080,6 @@ i915_gem_validate_context(struct drm_device *dev, struct drm_file *file, return ERR_PTR(-EIO); } - if (i915.enable_execlists && !ctx->engine[engine->id].state) { - int ret = intel_lr_context_deferred_alloc(ctx, engine); - if (ret) { - DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret); - return ERR_PTR(ret); - } - } - return ctx; } diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index c104015813d3..b0d20af38574 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -227,6 +227,8 @@ enum { #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 +static int execlists_context_deferred_alloc(struct intel_context *ctx, + struct intel_engine_cs *engine); static int intel_lr_context_pin(struct intel_context *ctx, struct intel_engine_cs *engine); @@ -672,8 +674,6 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request struct intel_engine_cs *engine = request->engine; int ret; - request->ringbuf = request->ctx->engine[engine->id].ringbuf; - if (i915.enable_guc_submission) { /* * Check that the GuC has space for the request before @@ -687,6 +687,14 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request return ret; } + if (request->ctx->engine[engine->id].state == NULL) { + ret = execlists_context_deferred_alloc(request->ctx, engine); + if (ret) + return ret; + } + + request->ringbuf = request->ctx->engine[engine->id].ringbuf; + ret = intel_lr_context_pin(request->ctx, engine); if (ret) return ret; @@ -2091,7 +2099,7 @@ logical_ring_init(struct intel_engine_cs *engine) if (ret) goto error; - ret = intel_lr_context_deferred_alloc(dctx, engine); + ret = execlists_context_deferred_alloc(dctx, engine); if (ret) goto error; @@ -2541,7 +2549,7 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine) } /** - * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context + * execlists_context_deferred_alloc() - create the LRC specific bits of a context * @ctx: LR context to create. * @ring: engine to be used with the context. * @@ -2553,9 +2561,8 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine) * * Return: non-zero on error. */ - -int intel_lr_context_deferred_alloc(struct intel_context *ctx, - struct intel_engine_cs *engine) +static int execlists_context_deferred_alloc(struct intel_context *ctx, + struct intel_engine_cs *engine) { struct drm_i915_gem_object *ctx_obj; uint32_t context_size; diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index b17ab79333aa..8bea937973f6 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -102,8 +102,6 @@ static inline void intel_logical_ring_emit_reg(struct intel_ringbuffer *ringbuf, void intel_lr_context_free(struct intel_context *ctx); uint32_t intel_lr_context_size(struct intel_engine_cs *engine); -int intel_lr_context_deferred_alloc(struct intel_context *ctx, - struct intel_engine_cs *engine); void intel_lr_context_unpin(struct intel_context *ctx, struct intel_engine_cs *engine);