| Message ID | 1461060455-14098-1-git-send-email-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 19/04/16 11:07, Chris Wilson wrote: > Move the i915_gem_l3_remap function such that it next to the context > switching, which is where we perform the L3 remap. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/i915_gem.c | 31 ------------------------------- > drivers/gpu/drm/i915/i915_gem_context.c | 31 +++++++++++++++++++++++++++++++ > 2 files changed, 31 insertions(+), 31 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 9ff73bf0e4ea..59419f10e76a 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -4729,37 +4729,6 @@ err: > return ret; > } > > -int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) > -{ > - struct intel_engine_cs *engine = req->engine; > - struct drm_device *dev = engine->dev; > - struct drm_i915_private *dev_priv = dev->dev_private; > - u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; > - int i, ret; > - > - if (!HAS_L3_DPF(dev) || !remap_info) > - return 0; > - > - ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3); > - if (ret) > - return ret; > - > - /* > - * Note: We do not worry about the concurrent register cacheline hang > - * here because no other code should access these registers other than > - * at initialization time. > - */ > - for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) { > - intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); > - intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i)); > - intel_ring_emit(engine, remap_info[i]); > - } > - > - intel_ring_advance(engine); > - > - return ret; > -} > - > void i915_gem_init_swizzling(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c > index 59d66b5bc8ad..68232d384902 100644 > --- a/drivers/gpu/drm/i915/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/i915_gem_context.c > @@ -643,6 +643,37 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) > return ret; > } > > +int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) > +{ > + struct intel_engine_cs *engine = req->engine; > + struct drm_device *dev = engine->dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; > + int i, ret; > + > + if (!HAS_L3_DPF(dev) || !remap_info) > + return 0; > + > + ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3); > + if (ret) > + return ret; > + > + /* > + * Note: We do not worry about the concurrent register cacheline hang > + * here because no other code should access these registers other than > + * at initialization time. > + */ > + for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) { > + intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); > + intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i)); > + intel_ring_emit(engine, remap_info[i]); > + } > + > + intel_ring_advance(engine); > + > + return ret; > +} > + > static inline bool skip_rcs_switch(struct intel_engine_cs *engine, > struct intel_context *to) > { > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Regards, Tvrtko
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 9ff73bf0e4ea..59419f10e76a 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4729,37 +4729,6 @@ err: return ret; } -int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) -{ - struct intel_engine_cs *engine = req->engine; - struct drm_device *dev = engine->dev; - struct drm_i915_private *dev_priv = dev->dev_private; - u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; - int i, ret; - - if (!HAS_L3_DPF(dev) || !remap_info) - return 0; - - ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3); - if (ret) - return ret; - - /* - * Note: We do not worry about the concurrent register cacheline hang - * here because no other code should access these registers other than - * at initialization time. - */ - for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) { - intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); - intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i)); - intel_ring_emit(engine, remap_info[i]); - } - - intel_ring_advance(engine); - - return ret; -} - void i915_gem_init_swizzling(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 59d66b5bc8ad..68232d384902 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -643,6 +643,37 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) return ret; } +int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) +{ + struct intel_engine_cs *engine = req->engine; + struct drm_device *dev = engine->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; + int i, ret; + + if (!HAS_L3_DPF(dev) || !remap_info) + return 0; + + ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3); + if (ret) + return ret; + + /* + * Note: We do not worry about the concurrent register cacheline hang + * here because no other code should access these registers other than + * at initialization time. + */ + for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) { + intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); + intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i)); + intel_ring_emit(engine, remap_info[i]); + } + + intel_ring_advance(engine); + + return ret; +} + static inline bool skip_rcs_switch(struct intel_engine_cs *engine, struct intel_context *to) {
Move the i915_gem_l3_remap function such that it next to the context switching, which is where we perform the L3 remap. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_gem.c | 31 ------------------------------- drivers/gpu/drm/i915/i915_gem_context.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 31 deletions(-)